CA2073151A1 - Method of and apparatus for detecting internal faults in information processing systems by pipeline processing - Google Patents
Method of and apparatus for detecting internal faults in information processing systems by pipeline processingInfo
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Abstract
ABSTRACT OF THE DISCLOSURE
An internal fault of an information processing system, particularly a primary processor for effecting information processing, is detected by pipeline process-ing using a redundant processor which is functionally identical to and effects the same information processing as the primary processor with a one-cycle delay with respect thereto. The information processing system includes a comparator having three pipeline stages. In the first pipeline stage, an input signal supplied to the primary processor and an output signal produced by the primary processor are introduced. In the second pipeline stage, the input signal is supplied to the redundant processor, which processes the supplied input signal.
The second stage simultaneously introduces the processed signal from the redundant processor as an output signal thereof and the output signal from the primary processor.
Finally, an output signal comparator in the third pipe-line stage compares the output signal from the primary processor and the output signal from the redundant proc-essor, and indicates an internal fault of the primary processor if the compared output signals disagree. The primary and redundant processors may comprise general-purpose processors. Internal faults of the information processing system can be detected without impairing the processing capability of the processors.
An internal fault of an information processing system, particularly a primary processor for effecting information processing, is detected by pipeline process-ing using a redundant processor which is functionally identical to and effects the same information processing as the primary processor with a one-cycle delay with respect thereto. The information processing system includes a comparator having three pipeline stages. In the first pipeline stage, an input signal supplied to the primary processor and an output signal produced by the primary processor are introduced. In the second pipeline stage, the input signal is supplied to the redundant processor, which processes the supplied input signal.
The second stage simultaneously introduces the processed signal from the redundant processor as an output signal thereof and the output signal from the primary processor.
Finally, an output signal comparator in the third pipe-line stage compares the output signal from the primary processor and the output signal from the redundant proc-essor, and indicates an internal fault of the primary processor if the compared output signals disagree. The primary and redundant processors may comprise general-purpose processors. Internal faults of the information processing system can be detected without impairing the processing capability of the processors.
Description
2~73~1 METHOD OF AND APPARATUS FOR DETECTING
INTERNAL FAULTS IN INFORMATION PROCESSING SYSTEMS
BY PIPELINE PROCESSING
BACKGROUND OF THE INVENTION
Field of the Invention The present invention relates to a method of and an apparatus for detecting internal faults in information processing systems.
Description of the Prior Art:
Heretofore, one known process of detecting internal faults in information processing systems has employed, in the information processing system, two processors which operate identically to process supplied signals. The two processors are supplied with the same input signal, and output signals from them are compared with each other. If the output signals do not coincide, then it is determined that the information processing system is suffering an internal fault.
FIG. 1 of the accompanying drawings shows a conventional information processing system with two such processors. The information processing system has comparator 6 to which an external signal output means (not shown) is connected through external interface bus 3 such as a cache bus or a memory bus. Comparator 6 is 207315~
connected to primary processor 21 and redundant processor 22 through processor buses 71, 72, respectively, each having the same interface as external interface bus 3.
Comparator 6 comprises input control circuit 61 and output comparing circuit 62. An input signal to be ; supplied from the external signal output means over external interface bus 3 to primary processor 21 and redundant processor 22 is applied to input control circuit 61 of comparator 6. The input signal is then outputted from input control circuit 61 over processor buses 71, 72 to primary processor 21 and redundant proc-essor 22. Primary processor 21 and redundant processor 22 then simultaneously process the input signal that has been applied thereto over processor buses 71, 72, respec-tively. Output comparing circuit 62 of comparator 6receives output signals from primary processor 21 and redundant processor 22 over respective processor buses 71, 72, and compares the received signals. The output ; signal from primary processor 21 is supplied from output comparing circuit 62 over internal bus 63 to external interface bus 3. If output comparing circuit 62 deter-mines that the output signals from primary processor 21 and redundant processor 22 do not coincide, then output comparing circuit 62 issues and transmits a fault signal over fault report line 5 to an external device, indicat-ing that an internal fault has occurred in the 20731~1 information processing system.
Another conventional information processing system as shown in FIG. 2 of the accompanying drawings has redundant processor 82 having a special function to achieve a redundant arrangement for the purpose of de-tecting internal faults. Redundant processor 82 prevents the transmission of an output signal to external inter-face bus 3, and receives as an input signal an output signal from primary processor 81. Redundant processor 82 compares the received input signal with the signal proc-essed thereby. In the event of disagreement between the compared signals, redundant processor 82 issues and transmits a fault signal over fault report line 5 to an external device, indicating that an internal fault has occurred in the information processing system.
With the information processing system shown in FIG. 1, however, since a logic circuit arrangement in comparator 6 is interposed between external interface bus 3 and primary and redundant processors 21, 22, if exter-nal interface bus 3 is a bus such as a cache bus whichrequires high-speed data transfer between itself and the processors, the interposed logic circuit arrangement causes a relatively large delay which impairs the proc-essing capability of primary and redundant processors 21, 2S 22.
The infarmation processing system illustrated in 20~3151 FIG. 2 is also problematic in that the special function to provide a redundant arrangement in redundant processor 82 prevents a general-purpose processor from being used as redundant processor 82.
SUMMARY OF THE INVENTION
In view of the foregoing drawbacks of the conventional information processing systems, it is an object of the present invention to provide a method of and an apparatus for detecting internal faults in infor-mation processing systems by pipeline processing, using a general-purpose processor for internal fault detection without impairing its processing capability.
To achieve the above object, there is provided in accordance with the present invention a method of - detecting an internal fault in an information processing system by pipeline processing having a primary processor for effecting information processing, with a redundant : processor which is functionally identical to and effects the same information processing as the primary processor, the method comprising the steps of introducing an input signal supplied to the primary processor and an output signal produced by the primary processor, supplying the input signal to the redundant processor to cause the redundant processor to process the input signal and, at the same time, introducing the processed signal from the redundant processor as an output signal from the redundant processor and the output signal from the pri-mary processor, and comparing the output signal from the primary processor and the output signal from the redun-dant processor, and indicating an internal fault of theprimary processor if the compared output signals disagree.
According to the present invention, there is also provided an information processing system having a function for detecting an internal fault thereof through pipeline processing, comprising a primary processor for effecting information processing, a redundant processor : which is functionally identical to and effects the same ; information processing as the primary processor, and a ; 15 comparator, the comparator comprising a first stage - including a primary processor interface for introducing : an input signal supplied to the primary processor and an output signal produced by the primary processor, a second stage including a redundant processor interface for supplying the input signal to the redundant processor to cause the redundant processor to process the input signal and introducing the processed signal from the redundant processor as an output signal from the redundant proces-sor, and a primary processor output interface for introducing the output signal from the primary processor from the primary processor interface at the same time 2073~
that the redundant processor interface introduces the output signal from the redundant processor, and a third stage including an output signa:L comparator for comparing the output signal from the primary processor and the output signal from the redundant processor, which are inputted from the second stage, and indicating an inter-nal fault of the information processing system if the compared output signals disagree.
The information processing system also includes an external interface bus interconnecting the primary processor and the external signal supply means, which bus is branched to the primary processor interface of the comparator.
The primary processor interface comprises a primary processor interface input unit for introducing the input signal supplied to the primary processor, and a primary processor interface output unit for introducing the output signal produced by the primary processor.
The redundant processor interface comprises a redundant processor signal supply unit for introducing the input signal supplied to the primary processor from the primary processor interface input unit and supplying ` the introduced input signal to the redundant processor, and a redundant processor signal output unit for intro-ducing the output signal from the redundant processor.
The above and other objects, features, and 20731~1 advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate a pre-ferred embodiment of the present invention by way of example.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a conventional information processing system with an apparatus for detecting an internal fault;
FIG. 2 is a block diagram of another convention-al information processing system with an apparatus for detecting an internal fault;
FIG. 3 is a block diagram of an example of an information processing system incorporating a method of detecting an internal fault by pipeline processing ac-cording to the present invention;
FIG. 4 is a block diagram illustrative of the - manner in which a signal is supplied from the comparator to the redundant processor in t}e information processing system shown in FIG. 3;
FIG. 5 is a block diagram illustrative of the manner in which an internal fault is detected by the comparator of FIG. 3;
FIG. 6(a) is a timing chart of input signals applied to primary and redundant processors as the input 20731 5~
signals vary in the first and second pipeline stages; and Fig. 6(b) is a timing chart of output signals produced from primary and redundant processors as the output signals vary in the first through third pipeline stages.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
As shown in FIG. 3, the information processing system basically comprises comparator 1, primary proces-sor 21 and redundant processor 22.
Comparator 1 comprises three pipeline stages for effecting pipeline processing, i.e., a first pipeline stage including primary processor interface 11, a second pipeline stage including primary processor output inter-face 12 and redundant processor interface 13, and a third pipeline stage including output signal comparator 14. As shown in FIGS. 4 and 5, primary processor interface 11 , .
~; has primary processor interface input unit lla and pri-mary processor interface output unit llb. Redundant processor interface 13 has redundant processor signal supply unit 13a and redundant processor signal output unit 13b.
Primary processor 21 comprises a processor for effecting normal information processing. Primary proces-sor 21 and primary processor interface 11 of comparator 1 are connected through external interface bus 3 to external signal supply unit 7 (see FIGS. 4 and 5) includ-ing a memory, an I/O device, and other devices.
Redundant processor 22, which serves to detect internal faults of the information processing system, particularly primary processor 21, has functions identi-cal to those of primary processor 21. Redundant processor 22 operates to process information in the same manner as primary processor 21, with a time delay of one cycle with respect to primary processor 21. Redundant processor 22 is connected to redundant processor inter-face 13 of comparator 1 through redundant processor bus 4 - which has the same interface structure and function as those of external interface bus 3.
Output signal comparator 14 is connected to primary processor output interface 12 and redundant processor interface 13. Output signal comparator 14 compares each output signal from primary processor output interface 12 and redundant processor interface 13. If the compared output signals do not coincide, then output signal comparator 14 issues and transmits a fault signal over fault report line 5, indicating that an internal fault has occurred in the information processing system.
; The process of detecting an internal fault in the information processing system shown in FIGS. 4 through 5 will be described below.
Primary processor 21, redundant processor 22 and comparator 1 are supplied with fundamental operation clock signal 6 (see FIGS. 4 and S) from a clock signal generator (not shown), and operate in synchronism with supplied fundamental operation clock signal 6. Primary 6 processor 21 receives necessary data and signals from external signal supply unit 7 through external interface bus 3 in response to control signal 31 such as a resource request signal that is produced by the primary processor 21. Primary processor 21 also receives control signals such as interrupt signals, reset signals, processor resource request signals, which are produced by external signal supply unit 7 of its own accord.
~` As shown in FIGS. 4, 5, 6(a), and 6(b), at time '~2~ (see FIGS. 6(a) and 6(b)), primary input signal #2 inputted from signal supply unit 7 is held in primary processor interface input unit lla and at the same time processed by primary processor 21. Then, the process signal is held as primary output signal #2 in primary processor interface output unit llb in the first pipeline stage. At time "3", primary input signal #2 is supplied from primary processor interface input unit lla in the first pipeline stage as redundant input signal #2 to redundant processor signal supply unit 13a in the second pipeline stage. ~edundant processor 22 receives neces-sary data and signals through redundant processor bus 4from redundant processor signal supply unit 13a in 20731~1 response to control signal 41 such as a resource request signal produced by redundant processor 22. Redundant processor 22 processes the received data and signals, and produces redundant output signal #2, which is held in redundant processor signal output unit 13b. Concurrent with this, primary output signal #2 is supplied from primary processor interface output unit llb in the first pipeline stage to primary processor output interface 12 in the second pipeline stage. At next time "4", output signal comparator 14 in the third pipeline stage compares primary output signal #2 and redundant output signal #2.
If primary output signal #2 and redundant output signal #2 coincide, then it is determined that the information processing system is normal. If primary output signal #2 and redundant output signal #2 do not coincide, then output signal comparator 14 produces result signal #2 as a fault signal indicating the occurrence of an internal fault and transmits result signal #2 over fault report - line 5 to an external device.
Successive primary input signals #3, #4, supplied from external signal supply unit 7 after primary ir.put signal #2 are similarly processed, held, and com-pared. If disagreement is detected between the compared signals, then output signal comparator 14 produces result 25 signals #3, #4, as fault signals which are transmit-ted over fault report line 5.
20731~1 As described above, reclundant processor 22 operates with a one-cycle delay relative to primary processor 21, and output signal comparator 14 compares output signals with a further one-cycle delay. General-purpose processors with no special functions may be usedas primary and redundant processors 21, 22 for the detec-tion of internal faults of the information processing system. Since no special logic circuit or mechanism is interposed between primary processor 22 and external interface bus 3, the information processing system oper-ates very speedily and reliably without impairing the processing capability of primary processor 22.
Although a certain preferred embodiment of the present invention has been shown and described in detail, it should be understood that various changes and modifi-: cations may be made therein without departing from the scope of the appended claims.
INTERNAL FAULTS IN INFORMATION PROCESSING SYSTEMS
BY PIPELINE PROCESSING
BACKGROUND OF THE INVENTION
Field of the Invention The present invention relates to a method of and an apparatus for detecting internal faults in information processing systems.
Description of the Prior Art:
Heretofore, one known process of detecting internal faults in information processing systems has employed, in the information processing system, two processors which operate identically to process supplied signals. The two processors are supplied with the same input signal, and output signals from them are compared with each other. If the output signals do not coincide, then it is determined that the information processing system is suffering an internal fault.
FIG. 1 of the accompanying drawings shows a conventional information processing system with two such processors. The information processing system has comparator 6 to which an external signal output means (not shown) is connected through external interface bus 3 such as a cache bus or a memory bus. Comparator 6 is 207315~
connected to primary processor 21 and redundant processor 22 through processor buses 71, 72, respectively, each having the same interface as external interface bus 3.
Comparator 6 comprises input control circuit 61 and output comparing circuit 62. An input signal to be ; supplied from the external signal output means over external interface bus 3 to primary processor 21 and redundant processor 22 is applied to input control circuit 61 of comparator 6. The input signal is then outputted from input control circuit 61 over processor buses 71, 72 to primary processor 21 and redundant proc-essor 22. Primary processor 21 and redundant processor 22 then simultaneously process the input signal that has been applied thereto over processor buses 71, 72, respec-tively. Output comparing circuit 62 of comparator 6receives output signals from primary processor 21 and redundant processor 22 over respective processor buses 71, 72, and compares the received signals. The output ; signal from primary processor 21 is supplied from output comparing circuit 62 over internal bus 63 to external interface bus 3. If output comparing circuit 62 deter-mines that the output signals from primary processor 21 and redundant processor 22 do not coincide, then output comparing circuit 62 issues and transmits a fault signal over fault report line 5 to an external device, indicat-ing that an internal fault has occurred in the 20731~1 information processing system.
Another conventional information processing system as shown in FIG. 2 of the accompanying drawings has redundant processor 82 having a special function to achieve a redundant arrangement for the purpose of de-tecting internal faults. Redundant processor 82 prevents the transmission of an output signal to external inter-face bus 3, and receives as an input signal an output signal from primary processor 81. Redundant processor 82 compares the received input signal with the signal proc-essed thereby. In the event of disagreement between the compared signals, redundant processor 82 issues and transmits a fault signal over fault report line 5 to an external device, indicating that an internal fault has occurred in the information processing system.
With the information processing system shown in FIG. 1, however, since a logic circuit arrangement in comparator 6 is interposed between external interface bus 3 and primary and redundant processors 21, 22, if exter-nal interface bus 3 is a bus such as a cache bus whichrequires high-speed data transfer between itself and the processors, the interposed logic circuit arrangement causes a relatively large delay which impairs the proc-essing capability of primary and redundant processors 21, 2S 22.
The infarmation processing system illustrated in 20~3151 FIG. 2 is also problematic in that the special function to provide a redundant arrangement in redundant processor 82 prevents a general-purpose processor from being used as redundant processor 82.
SUMMARY OF THE INVENTION
In view of the foregoing drawbacks of the conventional information processing systems, it is an object of the present invention to provide a method of and an apparatus for detecting internal faults in infor-mation processing systems by pipeline processing, using a general-purpose processor for internal fault detection without impairing its processing capability.
To achieve the above object, there is provided in accordance with the present invention a method of - detecting an internal fault in an information processing system by pipeline processing having a primary processor for effecting information processing, with a redundant : processor which is functionally identical to and effects the same information processing as the primary processor, the method comprising the steps of introducing an input signal supplied to the primary processor and an output signal produced by the primary processor, supplying the input signal to the redundant processor to cause the redundant processor to process the input signal and, at the same time, introducing the processed signal from the redundant processor as an output signal from the redundant processor and the output signal from the pri-mary processor, and comparing the output signal from the primary processor and the output signal from the redun-dant processor, and indicating an internal fault of theprimary processor if the compared output signals disagree.
According to the present invention, there is also provided an information processing system having a function for detecting an internal fault thereof through pipeline processing, comprising a primary processor for effecting information processing, a redundant processor : which is functionally identical to and effects the same ; information processing as the primary processor, and a ; 15 comparator, the comparator comprising a first stage - including a primary processor interface for introducing : an input signal supplied to the primary processor and an output signal produced by the primary processor, a second stage including a redundant processor interface for supplying the input signal to the redundant processor to cause the redundant processor to process the input signal and introducing the processed signal from the redundant processor as an output signal from the redundant proces-sor, and a primary processor output interface for introducing the output signal from the primary processor from the primary processor interface at the same time 2073~
that the redundant processor interface introduces the output signal from the redundant processor, and a third stage including an output signa:L comparator for comparing the output signal from the primary processor and the output signal from the redundant processor, which are inputted from the second stage, and indicating an inter-nal fault of the information processing system if the compared output signals disagree.
The information processing system also includes an external interface bus interconnecting the primary processor and the external signal supply means, which bus is branched to the primary processor interface of the comparator.
The primary processor interface comprises a primary processor interface input unit for introducing the input signal supplied to the primary processor, and a primary processor interface output unit for introducing the output signal produced by the primary processor.
The redundant processor interface comprises a redundant processor signal supply unit for introducing the input signal supplied to the primary processor from the primary processor interface input unit and supplying ` the introduced input signal to the redundant processor, and a redundant processor signal output unit for intro-ducing the output signal from the redundant processor.
The above and other objects, features, and 20731~1 advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate a pre-ferred embodiment of the present invention by way of example.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a conventional information processing system with an apparatus for detecting an internal fault;
FIG. 2 is a block diagram of another convention-al information processing system with an apparatus for detecting an internal fault;
FIG. 3 is a block diagram of an example of an information processing system incorporating a method of detecting an internal fault by pipeline processing ac-cording to the present invention;
FIG. 4 is a block diagram illustrative of the - manner in which a signal is supplied from the comparator to the redundant processor in t}e information processing system shown in FIG. 3;
FIG. 5 is a block diagram illustrative of the manner in which an internal fault is detected by the comparator of FIG. 3;
FIG. 6(a) is a timing chart of input signals applied to primary and redundant processors as the input 20731 5~
signals vary in the first and second pipeline stages; and Fig. 6(b) is a timing chart of output signals produced from primary and redundant processors as the output signals vary in the first through third pipeline stages.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
As shown in FIG. 3, the information processing system basically comprises comparator 1, primary proces-sor 21 and redundant processor 22.
Comparator 1 comprises three pipeline stages for effecting pipeline processing, i.e., a first pipeline stage including primary processor interface 11, a second pipeline stage including primary processor output inter-face 12 and redundant processor interface 13, and a third pipeline stage including output signal comparator 14. As shown in FIGS. 4 and 5, primary processor interface 11 , .
~; has primary processor interface input unit lla and pri-mary processor interface output unit llb. Redundant processor interface 13 has redundant processor signal supply unit 13a and redundant processor signal output unit 13b.
Primary processor 21 comprises a processor for effecting normal information processing. Primary proces-sor 21 and primary processor interface 11 of comparator 1 are connected through external interface bus 3 to external signal supply unit 7 (see FIGS. 4 and 5) includ-ing a memory, an I/O device, and other devices.
Redundant processor 22, which serves to detect internal faults of the information processing system, particularly primary processor 21, has functions identi-cal to those of primary processor 21. Redundant processor 22 operates to process information in the same manner as primary processor 21, with a time delay of one cycle with respect to primary processor 21. Redundant processor 22 is connected to redundant processor inter-face 13 of comparator 1 through redundant processor bus 4 - which has the same interface structure and function as those of external interface bus 3.
Output signal comparator 14 is connected to primary processor output interface 12 and redundant processor interface 13. Output signal comparator 14 compares each output signal from primary processor output interface 12 and redundant processor interface 13. If the compared output signals do not coincide, then output signal comparator 14 issues and transmits a fault signal over fault report line 5, indicating that an internal fault has occurred in the information processing system.
; The process of detecting an internal fault in the information processing system shown in FIGS. 4 through 5 will be described below.
Primary processor 21, redundant processor 22 and comparator 1 are supplied with fundamental operation clock signal 6 (see FIGS. 4 and S) from a clock signal generator (not shown), and operate in synchronism with supplied fundamental operation clock signal 6. Primary 6 processor 21 receives necessary data and signals from external signal supply unit 7 through external interface bus 3 in response to control signal 31 such as a resource request signal that is produced by the primary processor 21. Primary processor 21 also receives control signals such as interrupt signals, reset signals, processor resource request signals, which are produced by external signal supply unit 7 of its own accord.
~` As shown in FIGS. 4, 5, 6(a), and 6(b), at time '~2~ (see FIGS. 6(a) and 6(b)), primary input signal #2 inputted from signal supply unit 7 is held in primary processor interface input unit lla and at the same time processed by primary processor 21. Then, the process signal is held as primary output signal #2 in primary processor interface output unit llb in the first pipeline stage. At time "3", primary input signal #2 is supplied from primary processor interface input unit lla in the first pipeline stage as redundant input signal #2 to redundant processor signal supply unit 13a in the second pipeline stage. ~edundant processor 22 receives neces-sary data and signals through redundant processor bus 4from redundant processor signal supply unit 13a in 20731~1 response to control signal 41 such as a resource request signal produced by redundant processor 22. Redundant processor 22 processes the received data and signals, and produces redundant output signal #2, which is held in redundant processor signal output unit 13b. Concurrent with this, primary output signal #2 is supplied from primary processor interface output unit llb in the first pipeline stage to primary processor output interface 12 in the second pipeline stage. At next time "4", output signal comparator 14 in the third pipeline stage compares primary output signal #2 and redundant output signal #2.
If primary output signal #2 and redundant output signal #2 coincide, then it is determined that the information processing system is normal. If primary output signal #2 and redundant output signal #2 do not coincide, then output signal comparator 14 produces result signal #2 as a fault signal indicating the occurrence of an internal fault and transmits result signal #2 over fault report - line 5 to an external device.
Successive primary input signals #3, #4, supplied from external signal supply unit 7 after primary ir.put signal #2 are similarly processed, held, and com-pared. If disagreement is detected between the compared signals, then output signal comparator 14 produces result 25 signals #3, #4, as fault signals which are transmit-ted over fault report line 5.
20731~1 As described above, reclundant processor 22 operates with a one-cycle delay relative to primary processor 21, and output signal comparator 14 compares output signals with a further one-cycle delay. General-purpose processors with no special functions may be usedas primary and redundant processors 21, 22 for the detec-tion of internal faults of the information processing system. Since no special logic circuit or mechanism is interposed between primary processor 22 and external interface bus 3, the information processing system oper-ates very speedily and reliably without impairing the processing capability of primary processor 22.
Although a certain preferred embodiment of the present invention has been shown and described in detail, it should be understood that various changes and modifi-: cations may be made therein without departing from the scope of the appended claims.
Claims (7)
1. A method of detecting internal faults in information processing systems by pipeline processing having a primary processor for effecting information processing, with a redundant processor which is function-ally identical to and effects the same information processing as the primary processor, said method compris-ing the steps of:
introducing an input signal supplied to the primary processor and an output signal produced by the primary processor;
supplying said input signal to the redundant processor to cause the redundant processor to process said input signal and, at the same time, introducing the processed signal from the redundant processor as an output signal from the redundant processor and said output signal from said primary processor; and comparing said output signal from the primary processor and said output signal from the redundant processor, and indicating an internal fault of the pri-mary processor if the compared output signals disagree.
introducing an input signal supplied to the primary processor and an output signal produced by the primary processor;
supplying said input signal to the redundant processor to cause the redundant processor to process said input signal and, at the same time, introducing the processed signal from the redundant processor as an output signal from the redundant processor and said output signal from said primary processor; and comparing said output signal from the primary processor and said output signal from the redundant processor, and indicating an internal fault of the pri-mary processor if the compared output signals disagree.
2. An information processing system having a function for detecting internal faults thereof by pipe-line processing, comprising:
a primary processor for effecting information processing;
a redundant processor which is functionally identical to and effects the same information processing as said primary processor; and a comparator, said comparator comprising:
a first stage including a primary processor interface for introducing an input signal supplied to said primary processor and an output signal produced by said primary processor;
a second stage including a redundant processor interface for supplying said input signal to said redun-dant processor to cause said redundant processor to process said input signal and introducing the processed signal from said redundant processor as an output signal from said redundant processor, and a primary processor output interface for introducing said output signal from said primary processor from said primary processor inter-face at the same time that said redundant processor interface introduces said output signal from said redun-dant processor; and a third stage including an output signal comparator for comparing said output signal from said primary processor and said output signal from said redun-dant processor, which are inputted from said second stage, and indicating an internal fault of the informa-tion processing system if the compared output signals disagree.
a primary processor for effecting information processing;
a redundant processor which is functionally identical to and effects the same information processing as said primary processor; and a comparator, said comparator comprising:
a first stage including a primary processor interface for introducing an input signal supplied to said primary processor and an output signal produced by said primary processor;
a second stage including a redundant processor interface for supplying said input signal to said redun-dant processor to cause said redundant processor to process said input signal and introducing the processed signal from said redundant processor as an output signal from said redundant processor, and a primary processor output interface for introducing said output signal from said primary processor from said primary processor inter-face at the same time that said redundant processor interface introduces said output signal from said redun-dant processor; and a third stage including an output signal comparator for comparing said output signal from said primary processor and said output signal from said redun-dant processor, which are inputted from said second stage, and indicating an internal fault of the informa-tion processing system if the compared output signals disagree.
3. An information processing system according to claim 2, further including an external interface bus interconnecting said primary processor and an external signal supply means and being branched to said primary processor interface of said comparator.
4. An information processing system according to claim 2 or 3, wherein said primary processor interface comprises a primary processor interface input unit for introducing said input signal supplied to said primary processor, and a primary processor interface output unit for introducing said output signal produced by said primary processor.
5. An information processing system according to claim 4, wherein said redundant processor interface comprises a redundant processor signal supply unit for introducing said input signal supplied to said primary processor from said primary processor interface input unit and supplying said introduced input signal to said redundant processor, and a redundant processor signal output unit for introducing said output signal from said redundant processor.
6. An information processing system according to any one of claims 2 through 5, wherein said first, second, and third stages each comprise pipeline stages for effecting pipeline processing on said input and output signals.
7. An information processing system according to any one of claims 2 through 6, wherein said primary and/or redundant processors each comprise general-purpose processors.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP190748/1991 | 1991-07-04 | ||
| JP3190748A JP2646899B2 (en) | 1991-07-04 | 1991-07-04 | Internal failure detection method using pipeline |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2073151A1 true CA2073151A1 (en) | 1993-01-05 |
Family
ID=16263092
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2073151 Abandoned CA2073151A1 (en) | 1991-07-04 | 1992-07-03 | Method of and apparatus for detecting internal faults in information processing systems by pipeline processing |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2646899B2 (en) |
| CA (1) | CA2073151A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH086854A (en) * | 1993-12-23 | 1996-01-12 | Unisys Corp | Outboard-file-cache external processing complex |
| CA2549540C (en) | 2005-06-10 | 2008-12-09 | Hitachi, Ltd. | A task management control apparatus and method |
| JP4876093B2 (en) * | 2008-03-31 | 2012-02-15 | 株式会社日立製作所 | Control device task management device and control device task management method |
-
1991
- 1991-07-04 JP JP3190748A patent/JP2646899B2/en not_active Expired - Fee Related
-
1992
- 1992-07-03 CA CA 2073151 patent/CA2073151A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| JP2646899B2 (en) | 1997-08-27 |
| JPH0512052A (en) | 1993-01-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Dead |