JPH0512052A - Internal fault detection system using pipe line - Google Patents

Abstract

PURPOSE:To realize a function detecting the internal fault without damaging the processing ability of a processor by using a general processor. CONSTITUTION:A basic processor 21 performs the normal information processing, and a redundant processor 22 having the same function as a basic processor 21 performs the same information processing to the basic processor 21 delayed by one cycle. A comparator 1 constituting three-staged pipe line draws all the input/output signals of the basic processor 21, and draws the output signal of the redundant processor 22 as soon as a two-staged redundant processor interface part 12 outputs the input signal of the basic processor 21 to the redundant processor 22. A three-staged output signal comparison part 13 compares the output signal of the basic processor 21 with the output signal of the redundant processor 22 to detect the internal fault.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault detection system for an information processing apparatus, and more particularly to a pipeline internal fault detection system.

[0002]

2. Description of the Related Art Conventionally, in an information processing apparatus equipped with two processors and performing the same operation to detect an internal failure, the same input signal is applied to both processors at the same time and output signals are instantaneously output by a comparator. It was a method of comparison.

For example, in a conventional information processing apparatus as shown in FIG. 2, an external interface bus 3 such as a cache bus or a memory bus is connected to a comparator 6, and the comparator 6 is connected to the external interface bus 3. It is connected to the basic processor 21 and the redundant processor 22 via processor buses 71 and 72 having an equivalent interface. Basic processor 2 from external interface bus 3
1 and the input signals to the redundant processor 22 are input to the input control circuit 61 of the comparator 6, and the input control circuit 61
Is output to the basic processor 21 and the redundant processor 22 via the processor buses 71 and 72. The basic processor 21 and the redundant processor 22 perform the same information processing according to the input signals input via the processor buses 71 and 72, and output the output signals to the processor buses 71 and 72. The output signals from the basic processor 21 and the redundant processor 22 are input to the output comparison circuit 62 via the processor buses 71 and 72,
Both output signals are compared. The output signal to the outside is output from the output comparison circuit 62 to the external interface bus 3 via the internal bus 63. When the output signals from the basic processor 21 and the redundant processor 22 do not match, the output comparison circuit 62 reports the occurrence of an internal fault to the outside through the fault reporting line 5.

Further, in the conventional information processing apparatus as shown in FIG. 3, a redundant processor 82 having a special function for taking a redundant configuration for detecting an internal failure is used. The redundant processor 82 uses the external interface bus 3
Output signal from the basic processor 81 is received as an input signal and compared with its own processing result, and if a mismatch is detected, an internal failure is externally generated by the failure report line 5. To report.

[0005]

In the above-described conventional information processing apparatus, in the case of the information processing apparatus shown in FIG. 2, the comparator 6 is provided between the basic processor 21 and the redundant processor 22 and the external interface bus 3. When the external interface bus 3 is a bus that requires high-speed data transfer with a processor such as a cache bus, the delay due to the intervening logic circuit system increases and the basic processor 21 and the redundant processor are redundant. There is a problem that the original processing capability of the processor 22 may be impaired.

Further, in the case of the information processing apparatus shown in FIG. 3, since it is necessary to previously install a function for redundant configuration in the redundant processor 82, the redundant processor 82.
However, there is a problem that a general-purpose processor cannot be used.

In view of the above points, an object of the present invention is to provide an internal fault detection method using a pipeline, which uses a general-purpose processor and realizes an internal fault detection function without impairing the processing capability of the processor. To do.

[0008]

An internal fault detection method using a pipeline according to the present invention is a basic processor that performs normal information processing, and has the same function as this basic processor and is delayed by one cycle with respect to the basic processor. A redundant processor that performs the same information processing, a first stage that pulls in all the input / output signals of the basic processor, and a second stage that outputs the input signal of the basic processor to the redundant processor and at the same time pulls the output signal of the redundant processor. Dan and the first
A comparator forming a three-stage pipeline including a third stage for detecting an internal fault by comparing the output signal of the basic processor pulled in at the second stage with the output signal of the redundant processor pulled in at the second stage; Have.

[0009]

In the internal fault detection method using the pipeline of the present invention, the basic processor performs normal information processing, and the redundant processor having the same function as the basic processor performs the same information processing with a delay of one cycle from the basic processor. The first stage of the comparator forming the three-stage pipeline draws all the input / output signals of the basic processor, and the second stage outputs the input signal of the basic processor to the redundant processor and at the same time the output signal of the redundant processor. , The third stage pulls in the first stage output signal of the basic processor and the second stage
An internal fault is detected by comparing the output signal of the redundant processor pulled in at each stage.

[0010]

The present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an internal fault detection system using a pipeline according to an embodiment of the present invention. The internal fault detection method using the pipeline of the present embodiment is composed of a comparator 1, a basic processor 21, and a redundant processor 22 as its main components.

The comparator 1 is a three-stage pipeline consisting of a first-stage basic processor interface unit 11, a second-stage redundant processor interface unit 12, and a third-stage output signal comparison unit 13. It is configured. The output signal comparison unit 13 of the third stage is connected to the fault report line 5.

The basic processor 21 is a processor for performing normal information processing, and the basic processor interface section 1 of the first stage of the comparator 1 is connected via the external interface bus 3.
It is connected to 1.

The redundant processor 22 is a processor which has the same function as that of the basic processor 21 to detect an internal failure and performs the same information processing with a delay of one cycle from the basic processor 21, and is equivalent to the external interface bus 3. Redundant processor interface unit 12 of the second stage of the comparator 1 via the redundant processor bus 4 having the interface
It is connected to the.

Next, the operation of the internal fault detection system by the pipeline of the present embodiment having the above-mentioned configuration will be described.

The first-stage basic processor interface section 11 takes in all input / output signals from the external interface bus 3 to the basic processor 21. All the input / output signals fetched by the first-stage basic processor interface unit 11 are sent to the second-stage redundant processor interface unit 12.

The redundant processor interface section 12 of the second stage is the basic processor interface section 11 of the first stage.
Basic processor 2 of the input / output signals sent from
The input signal to 1 is supplied to the redundant processor 22 via the redundant processor bus 4. At the same time, the second-stage redundant processor interface unit 12 takes in the output signal output from the redundant processor 22 via the redundant processor bus 4. The output signal of the basic processor 21 sent from the first-stage basic processor interface section 11 and the second-stage redundant processor interface section 12
The output signal of the redundant processor 22 surrounded by (4) is sent to the output signal comparison unit 13 of the third stage.

The output signal comparing section 13 of the third stage compares the output signal of the basic processor 21 and the output signal of the redundant processor 22 sent from the redundant processor interface section 12 of the second stage, and when they do not match. There is a trouble report line 5
Report the occurrence of internal failure to the outside via.

The processing from the basic processor interface section 11 of the first stage to the output signal comparing section 13 of the third stage is shifted every bus cycle of the external interface bus 3 and the basic processor 21 and the redundant processor 22 are shifted. Pipeline processing without impairing the processing speed of.

[0020]

As described above, the present invention performs the same information processing by delaying the input signal of the basic processor by one cycle from the first stage for pulling in all the input / output signals of the basic processor. The second signal which outputs to the redundant processor and at the same time pulls in the output signal of the redundant processor
Comparator with a three-stage pipeline consisting of a third stage for detecting an internal fault by comparing the output signal of the basic processor pulled in at the first stage with the output signal of the redundant processor pulled in at the second stage With the above configuration, it is possible to detect an internal failure by using a general-purpose processor without deteriorating the processing capability of the processor.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an internal fault detection method using a pipeline according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a conventional internal failure detection method.

FIG. 3 is a block diagram showing another example of a conventional internal fault detection method.

[Explanation of symbols]

 1 Comparator 3 External Interface Bus 4 Redundant Processor Bus 5 Fault Report Line 11 Basic Processor Interface Section 12 Redundant Processor Interface Section 13 Output Signal Comparison Section 21 Basic Processor 22 Redundant Processor

Claims (1)

Claim: What is claimed is: 1. A basic processor that performs normal information processing, and a redundant processor that has the same function as this basic processor and that performs the same information processing with a delay of one cycle from the basic processor. A first stage for pulling in all input / output signals of the basic processor; a second stage for outputting the input signal of the basic processor to the redundant processor; and a second stage for simultaneously pulling in the output signal of the redundant processor; And a comparator forming a three-stage pipeline including a third stage for detecting an internal fault by comparing the output signal of the basic processor with the output signal of the redundant processor pulled in by the second stage. An internal failure detection method by a pipeline.