JPH0535368A - Reset circuit - Google Patents

Abstract

PURPOSE:To obtain the reset circuit which can recognize a fault or can analyze it even when resetting a circuit equipped with a microprocessor or a system. CONSTITUTION:This circuit is equipped with a first reset circuit system to reset only a microprocessor 7 and the circuit related to this microprocessor according to a state holding reset signal 1 and a second reset circuit system to reset the entire circuit or system equipped with the microprocessor according to a full system reset signal 2 and in the first reset circuit system, the fault state of the unreset circuit can be detected by the reset microprocessor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit or system using a microprocessor such as a control circuit or an electronic computer, and more particularly to a reset circuit thereof.

[0002]

2. Description of the Related Art Generally, a circuit or system using a microprocessor is provided with a reset circuit for returning the circuit or system to an initial state when a failure occurs. This conventional reset circuit is configured to reset all peripheral circuits such as an input / output circuit including a control unit including a microprocessor.

[0003]

The above-mentioned conventional reset circuit resets the entire circuit or system from a faulty state to a normal state when resetting is performed, so that it is possible to know the place or state where a fault has occurred after resetting. Or, there is a problem that analysis becomes impossible. An object of the present invention is to provide a reset circuit capable of knowing or analyzing a failure point even after resetting.

[0004]

The reset circuit of the present invention includes a first reset circuit system for resetting only a microprocessor and circuits closely related to it by a state holding reset signal, and a microprocessor by a whole system reset signal. Second to reset all circuits or systems including
And the first reset circuit system is configured so that the fault condition of the circuit which is not reset by the reset microprocessor can be detected.

[0005]

According to the present invention, by using the first reset circuit system, it is possible to detect the fault condition of the circuit which is not reset by the reset microprocessor and confirm and analyze the fault condition.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. The control unit includes a microprocessor 7, a port 6 connected to the microprocessor 7 via respective address and data buses 10, a RAM 8 and an RO.
It has M9. A state hold reset signal 1 and a system reset signal 2 are input to the microprocessor 7 through an OR gate 3, respectively. Flip-flops 4 and 5 are connected to the port 6, respectively, and the signals 1 and 2 are input to the flip-flops 4 and 5, respectively. Further, outside the control unit, a plurality of I / O circuits 11 are connected via the bus 10. Each of these I / O circuits 11 is provided with a buffer 12 and receives the whole system reset signal 2 of the signals.

According to this configuration, even if either the state holding reset signal 1 or the system reset signal 2 is input,
The microprocessor 7 is reset. When a failure occurs in the entire system, the state holding reset signal 1 is first used to initialize only the control section, and at the same time, the flip-flop 4 is set. Since the microprocessor 7 is enabled by the state-holding reset signal 1, the microprocessor 7 is used and the ROM
The port 6 is read by the program stored in 9 to check the states of the flip-flops 4 and 5 to know that the state-holding reset has been performed.
After that, the RAM 8 is cleared. Next, the microprocessor 7 reads the fault status of each buffer 12 through the bus 10 in order to know the fault status of each I / O 11, transfers it to the area of the RAM 8 which stores the fault status, and the processing of the microprocessor 7 is performed. finish.

Next, the system reset signal 2 is applied to the entire system to initialize the entire system. In the control unit, when the system reset signal 2 is input, the microprocessor 7 is reset, and the system reset signal 2 is latched in the flip-flop 5 at the same time. The initialized microprocessor 7 reads the port 6 and checks the states of the flip-flops 4 and 5 to know that the system reset has been performed. The microprocessor 7
Initializes the control unit and the entire system. At this time, each I
The area of the RAM 8 that stores the failure status of / O11 is not cleared.

FIG. 2 is a flow chart showing the operation of the reset circuit of FIG. As a microprocessor,
As soon as it is reset, it is determined whether it is a state holding reset or a system reset. When the state hold reset is input, the microprocessor clears the RAM and writes the fault status of each I / O to the RAM. In the case of resetting the entire system, the areas other than the RAM area in which the failure status is stored are cleared and the initial processing of each hardware is performed. Then return to the system program.

[0010]

As described above, according to the present invention, when a failure occurs in the circuit or system using the microprocessor, the first reset circuit system allows only the microprocessor and the circuits closely related thereto. A faulty location can be identified using a microprocessor that has been reset and enabled. Also, store this fault in memory,
By resetting the circuits other than the memory area in which the failure is stored in the second reset circuit system, it is possible to know the failure occurrence state from the normalized circuit or system.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a reset circuit of the present invention.

FIG. 2 is a flowchart showing a reset operation according to the present invention.

[Explanation of symbols]

 1 state hold reset signal 2 whole system reset signal 4,5 flip-flop 6 port 7 microprocessor 8 RAM 9 ROM 10 bus 11 I / O

Claims (1)

Claim: What is claimed is: 1. A reset circuit for resetting a circuit or system including a microprocessor, wherein a first reset circuit resets only the microprocessor and a circuit deeply related thereto by a state holding reset signal. System, and a second reset circuit system for resetting all circuits or systems including the microprocessor by a reset signal for the entire system, in the first reset circuit system, a failure state of the circuit not reset by the reset microprocessor A reset circuit characterized in that it is configured to detect