CA2058933A1 - Methode de reinitialisation en cas de defaillance d'un module d'adaptation et ordinateur utilisant cette methode - Google Patents

Methode de reinitialisation en cas de defaillance d'un module d'adaptation et ordinateur utilisant cette methode

Info

Publication number
CA2058933A1
CA2058933A1 CA2058933A CA2058933A CA2058933A1 CA 2058933 A1 CA2058933 A1 CA 2058933A1 CA 2058933 A CA2058933 A CA 2058933A CA 2058933 A CA2058933 A CA 2058933A CA 2058933 A1 CA2058933 A1 CA 2058933A1
Authority
CA
Canada
Prior art keywords
adaptor module
adaptor
module
faulty
computer system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2058933A
Other languages
English (en)
Other versions
CA2058933C (fr
Inventor
Youichi Nakamura
Makoto Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2058933A1 publication Critical patent/CA2058933A1/fr
Application granted granted Critical
Publication of CA2058933C publication Critical patent/CA2058933C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1438—Restarting or rejuvenating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
CA002058933A 1990-04-13 1991-04-12 Methode de reinitialisation en cas de defaillance d'un module d'adaptation et ordinateur utilisant cette methode Expired - Fee Related CA2058933C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP02-098818 1990-04-13
JP9881890 1990-04-13

Publications (2)

Publication Number Publication Date
CA2058933A1 true CA2058933A1 (fr) 1991-10-14
CA2058933C CA2058933C (fr) 1996-10-29

Family

ID=14229898

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002058933A Expired - Fee Related CA2058933C (fr) 1990-04-13 1991-04-12 Methode de reinitialisation en cas de defaillance d'un module d'adaptation et ordinateur utilisant cette methode

Country Status (6)

Country Link
US (1) US5321830A (fr)
EP (1) EP0477385B1 (fr)
AU (1) AU637227B2 (fr)
CA (1) CA2058933C (fr)
DE (1) DE69128391T2 (fr)
WO (1) WO1991016678A1 (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5390324A (en) * 1992-10-02 1995-02-14 Compaq Computer Corporation Computer failure recovery and alert system
JP2886093B2 (ja) * 1994-07-28 1999-04-26 株式会社日立製作所 障害処理方法および情報処理システム
KR100244836B1 (ko) * 1995-11-02 2000-02-15 포만 제프리 엘 컴퓨터시스템 및 다수의 기능카드 중 한개의 기능카드를 격리하는 방법
US6049672A (en) * 1996-03-08 2000-04-11 Texas Instruments Incorporated Microprocessor with circuits, systems, and methods for operating with patch micro-operation codes and patch microinstruction codes stored in multi-purpose memory structure
US6141740A (en) * 1997-03-03 2000-10-31 Advanced Micro Devices, Inc. Apparatus and method for microcode patching for generating a next address
US5983337A (en) * 1997-06-12 1999-11-09 Advanced Micro Devices, Inc. Apparatus and method for patching an instruction by providing a substitute instruction or instructions from an external memory responsive to detecting an opcode of the instruction
US6085332A (en) * 1998-08-07 2000-07-04 Mylex Corporation Reset design for redundant raid controllers
TW406507B (en) * 1998-10-30 2000-09-21 Kim Man Ki SECS-I and HSMS converting method
US6438664B1 (en) 1999-10-27 2002-08-20 Advanced Micro Devices, Inc. Microcode patch device and method for patching microcode using match registers and patch routines
JP4443067B2 (ja) * 2001-04-26 2010-03-31 富士通マイクロエレクトロニクス株式会社 プロセッサおよびそのリセット制御方法
US6963942B2 (en) * 2001-12-04 2005-11-08 Motorola, Inc. High availability system and method for improved intialization
JP2010140361A (ja) * 2008-12-12 2010-06-24 Fujitsu Microelectronics Ltd コンピュータシステム及び異常検出回路

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943768B2 (ja) * 1980-06-13 1984-10-24 富士通株式会社 チヤネル装置の初期起動方式
JPS5714926A (en) * 1980-06-30 1982-01-26 Nec Corp Reset controlling system of input/output device
US4589090A (en) * 1982-09-21 1986-05-13 Xerox Corporation Remote processor crash recovery
US4901232A (en) * 1983-05-19 1990-02-13 Data General Corporation I/O controller for controlling the sequencing of execution of I/O commands and for permitting modification of I/O controller operation by a host processor
JPS62209627A (ja) * 1986-03-10 1987-09-14 Nec Corp デ−タ処理装置
US4802119A (en) * 1987-03-17 1989-01-31 Motorola, Inc. Single chip microcomputer with patching and configuration controlled by on-board non-volatile memory
JPH01217614A (ja) * 1988-02-26 1989-08-31 Fujitsu Ltd システムリセット制御方式
DE3886529T2 (de) * 1988-08-27 1994-06-30 Ibm Einrichtung in einem Datenverarbeitungssystem zur System-Initialisierung und -Rückstellung.
CA2027799A1 (fr) * 1989-11-03 1991-05-04 David A. Miller Methode et dispositif pour reinitialiser individuellement les processeurs et les controleurs d'antememoire dans les systeme multiprocesseurs

Also Published As

Publication number Publication date
EP0477385B1 (fr) 1997-12-10
AU7661791A (en) 1991-11-11
EP0477385A1 (fr) 1992-04-01
EP0477385A4 (en) 1993-02-24
US5321830A (en) 1994-06-14
DE69128391T2 (de) 1998-04-02
WO1991016678A1 (fr) 1991-10-31
AU637227B2 (en) 1993-05-20
CA2058933C (fr) 1996-10-29
DE69128391D1 (de) 1998-01-22

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Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed
MKLA Lapsed

Effective date: 20040413