CA2044361A1 - Dispositif et methode de stockage a transistors bipolaires - Google Patents

Dispositif et methode de stockage a transistors bipolaires

Info

Publication number
CA2044361A1
CA2044361A1 CA2044361A CA2044361A CA2044361A1 CA 2044361 A1 CA2044361 A1 CA 2044361A1 CA 2044361 A CA2044361 A CA 2044361A CA 2044361 A CA2044361 A CA 2044361A CA 2044361 A1 CA2044361 A1 CA 2044361A1
Authority
CA
Canada
Prior art keywords
memory cell
bipolar transistor
state elements
transistor memory
pair
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2044361A
Other languages
English (en)
Other versions
CA2044361C (fr
Inventor
Robert M. Reinschmidt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=24180252&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=CA2044361(A1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of CA2044361A1 publication Critical patent/CA2044361A1/fr
Application granted granted Critical
Publication of CA2044361C publication Critical patent/CA2044361C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
    • G11C11/4113—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access to base or collector of at least one of said transistors, e.g. via access diodes, access transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
CA002044361A 1990-06-29 1991-06-11 Dispositif et methode de stockage a transistors bipolaires Expired - Fee Related CA2044361C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US54639590A 1990-06-29 1990-06-29
US546,395 1990-06-29

Publications (2)

Publication Number Publication Date
CA2044361A1 true CA2044361A1 (fr) 1991-12-30
CA2044361C CA2044361C (fr) 1996-09-24

Family

ID=24180252

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002044361A Expired - Fee Related CA2044361C (fr) 1990-06-29 1991-06-11 Dispositif et methode de stockage a transistors bipolaires

Country Status (6)

Country Link
US (1) US5289409A (fr)
JP (1) JPH05151779A (fr)
CA (1) CA2044361C (fr)
DE (1) DE4121445C2 (fr)
FR (1) FR2664081A1 (fr)
GB (1) GB2247550B (fr)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3288189B2 (ja) * 1994-12-12 2002-06-04 三菱電機株式会社 スタティックランダムアクセスメモリ
JPH1139880A (ja) * 1997-07-16 1999-02-12 Mitsubishi Electric Corp 半導体記憶装置
US7196925B1 (en) * 2004-08-26 2007-03-27 Cypress Semiconductor Corporation Memory array with current limiting device for preventing particle induced latch-up
US8837204B2 (en) * 2009-02-15 2014-09-16 NDEP Technologies Ltd. Four-transistor and five-transistor BJT-CMOS asymmetric SRAM cells
US8526220B2 (en) * 2011-06-12 2013-09-03 International Business Machines Corporation Complementary SOI lateral bipolar for SRAM in a low-voltage CMOS platform
US8929133B2 (en) * 2012-12-02 2015-01-06 International Business Machines Corporation Complementary SOI lateral bipolar for SRAM in a CMOS platform
US9460771B2 (en) * 2014-09-25 2016-10-04 Kilopass Technology, Inc. Two-transistor thyristor SRAM circuit and methods of operation
CN106030718A (zh) * 2014-09-25 2016-10-12 克劳帕斯科技有限公司 保持和刷新闸流晶体管随机存取存储器中的数据的方法
US9741413B2 (en) 2014-09-25 2017-08-22 Kilopass Technology, Inc. Methods of reading six-transistor cross-coupled thyristor-based SRAM memory cells
US9449669B2 (en) 2014-09-25 2016-09-20 Kilopass Technology, Inc. Cross-coupled thyristor SRAM circuits and methods of operation
EP3149736A4 (fr) * 2014-09-25 2018-01-24 Kilopass Technology, Inc. Circuits sram d'assistance à l'écriture et procédés de fonctionnement
US9613968B2 (en) 2014-09-25 2017-04-04 Kilopass Technology, Inc. Cross-coupled thyristor SRAM semiconductor structures and methods of fabrication
US9496021B2 (en) * 2014-09-25 2016-11-15 Kilopass Technology, Inc. Power reduction in thyristor random access memory
US20160093624A1 (en) 2014-09-25 2016-03-31 Kilopass Technology, Inc. Thyristor Volatile Random Access Memory and Methods of Manufacture
US9564441B2 (en) * 2014-09-25 2017-02-07 Kilopass Technology, Inc. Two-transistor SRAM semiconductor structure and methods of fabrication
US9530482B2 (en) 2014-09-25 2016-12-27 Kilopass Technology, Inc. Methods of retaining and refreshing data in a thyristor random access memory
US9564199B2 (en) 2014-09-25 2017-02-07 Kilopass Technology, Inc. Methods of reading and writing data in a thyristor random access memory

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3231763A (en) * 1963-10-07 1966-01-25 Bunker Ramo Bistable memory element
DE1524892B1 (de) * 1967-12-15 1970-09-03 Ibm Deutschland Halbleiterspeicherzelle mit kreuzgekoppelten Multie mittertransistoren
US3863229A (en) * 1973-06-25 1975-01-28 Ibm Scr (or scs) memory array with internal and external load resistors
US3918033A (en) * 1974-11-11 1975-11-04 Ibm SCR memory cell
GB1565146A (en) * 1976-08-16 1980-04-16 Fairchild Camera Instr Co Random access momory cells
US4288862A (en) * 1977-12-21 1981-09-08 Nippon Telegraph And Telephone Public Corp. Memory circuit
US4297598A (en) * 1979-04-05 1981-10-27 General Instrument Corporation I2 L Sensing circuit with increased sensitivity
DE2944141A1 (de) * 1979-11-02 1981-05-14 Ibm Deutschland Gmbh, 7000 Stuttgart Monolithisch integrierte speicheranordnung
US4287575A (en) * 1979-12-28 1981-09-01 International Business Machines Corporation High speed high density, multi-port random access memory cell
JPS58147887A (ja) * 1982-02-26 1983-09-02 Mitsubishi Electric Corp 半導体記憶装置
JPS62177961A (ja) * 1986-01-31 1987-08-04 Hitachi Ltd 半導体装置
US4769785A (en) * 1986-06-02 1988-09-06 Advanced Micro Devices, Inc. Writing speed of SCR-based memory cells
US4858181A (en) * 1987-07-07 1989-08-15 Texas Instruments Incorporated Fast recovery PNP loaded bipolar static RAM memory cell with an independent current path

Also Published As

Publication number Publication date
DE4121445C2 (de) 1996-09-12
JPH05151779A (ja) 1993-06-18
CA2044361C (fr) 1996-09-24
DE4121445A1 (de) 1992-01-23
US5289409A (en) 1994-02-22
GB2247550B (en) 1994-08-03
FR2664081A1 (fr) 1992-01-03
FR2664081B1 (fr) 1997-02-14
GB9112428D0 (en) 1991-07-31
GB2247550A (en) 1992-03-04

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