CA1228674A - Redundant page identification for a catalogued memory - Google Patents

Redundant page identification for a catalogued memory

Info

Publication number
CA1228674A
CA1228674A CA000481990A CA481990A CA1228674A CA 1228674 A CA1228674 A CA 1228674A CA 000481990 A CA000481990 A CA 000481990A CA 481990 A CA481990 A CA 481990A CA 1228674 A CA1228674 A CA 1228674A
Authority
CA
Canada
Prior art keywords
address
memory
cache
directory
page
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000481990A
Other languages
English (en)
French (fr)
Inventor
Jerry D. Dixon
Robert H. Farrell
Gerald A. Marazas
Andrew B. Mcneill, Jr.
Gerald U. Merckel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA1228674A publication Critical patent/CA1228674A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1064Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
CA000481990A 1984-11-02 1985-05-21 Redundant page identification for a catalogued memory Expired CA1228674A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US667,520 1984-11-02
US06/667,520 US4637024A (en) 1984-11-02 1984-11-02 Redundant page identification for a catalogued memory

Publications (1)

Publication Number Publication Date
CA1228674A true CA1228674A (en) 1987-10-27

Family

ID=24678548

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000481990A Expired CA1228674A (en) 1984-11-02 1985-05-21 Redundant page identification for a catalogued memory

Country Status (5)

Country Link
US (1) US4637024A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0180821B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS61114356A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CA (1) CA1228674A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3585496D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1241768A (en) * 1984-06-22 1988-09-06 Miyuki Ishida Tag control circuit for buffer storage
US4972316A (en) * 1987-03-30 1990-11-20 International Business Machines Corporation Method of handling disk sector errors in DASD cache
US4991090A (en) * 1987-05-18 1991-02-05 International Business Machines Corporation Posting out-of-sequence fetches
US6092153A (en) * 1988-11-14 2000-07-18 Lass; Stanley Edwin Subsettable top level cache
US5329629A (en) * 1989-07-03 1994-07-12 Tandem Computers Incorporated Apparatus and method for reading, writing, and refreshing memory with direct virtual or physical access
US5195100A (en) * 1990-03-02 1993-03-16 Micro Technology, Inc. Non-volatile memory storage of write operation identifier in data sotrage device
US5233618A (en) * 1990-03-02 1993-08-03 Micro Technology, Inc. Data correcting applicable to redundant arrays of independent disks
US5138710A (en) * 1990-04-25 1992-08-11 Unisys Corporation Apparatus and method for providing recoverability in mass storage data base systems without audit trail mechanisms
US5361345A (en) * 1991-09-19 1994-11-01 Hewlett-Packard Company Critical line first paging system
US5317713A (en) * 1991-09-19 1994-05-31 Quantum Corporation Micro-winchester disk drive having on-board segmented cache memory
JP3181001B2 (ja) * 1993-06-01 2001-07-03 インターナショナル・ビジネス・マシーンズ・コーポレ−ション キャッシュ・メモリ・システム並びにキャッシュ・メモリ・アクセス方法及びシステム
JP3264465B2 (ja) * 1993-06-30 2002-03-11 株式会社日立製作所 記憶システム
US5586253A (en) * 1994-12-15 1996-12-17 Stratus Computer Method and apparatus for validating I/O addresses in a fault-tolerant computer system
US5649155A (en) * 1995-03-31 1997-07-15 International Business Machines Corporation Cache memory accessed by continuation requests
JP2928165B2 (ja) * 1996-08-16 1999-08-03 日本電気マイコンテクノロジー株式会社 Atmスイッチ
US5883904A (en) * 1997-04-14 1999-03-16 International Business Machines Corporation Method for recoverability via redundant cache arrays
US6098190A (en) * 1998-08-04 2000-08-01 Hewlett-Packard Co. Method and apparatus for use of a host address to validate accessed data
US6463509B1 (en) * 1999-01-26 2002-10-08 Motive Power, Inc. Preloading data in a cache memory according to user-specified preload criteria
US6370614B1 (en) 1999-01-26 2002-04-09 Motive Power, Inc. I/O cache with user configurable preload
US6862689B2 (en) 2001-04-12 2005-03-01 Stratus Technologies Bermuda Ltd. Method and apparatus for managing session information
US6802022B1 (en) 2000-04-14 2004-10-05 Stratus Technologies Bermuda Ltd. Maintenance of consistent, redundant mass storage images
US6928521B1 (en) 2000-08-01 2005-08-09 International Business Machines Corporation Method, system, and data structures for using metadata in updating data in a storage device
US6948010B2 (en) * 2000-12-20 2005-09-20 Stratus Technologies Bermuda Ltd. Method and apparatus for efficiently moving portions of a memory block
US6766413B2 (en) 2001-03-01 2004-07-20 Stratus Technologies Bermuda Ltd. Systems and methods for caching with file-level granularity
US6874102B2 (en) * 2001-03-05 2005-03-29 Stratus Technologies Bermuda Ltd. Coordinated recalibration of high bandwidth memories in a multiprocessor computer
JP4374834B2 (ja) * 2002-08-12 2009-12-02 セイコーエプソン株式会社 カートリッジおよび記録装置
DE10327549A1 (de) * 2003-06-18 2005-01-13 Robert Bosch Gmbh Verfahren und Vorrichtung zur Fehlererkennung für einen Cachespeicher und entsprechender Cachespeicher
US20060222126A1 (en) * 2005-03-31 2006-10-05 Stratus Technologies Bermuda Ltd. Systems and methods for maintaining synchronicity during signal transmission
US20060222125A1 (en) * 2005-03-31 2006-10-05 Edwards John W Jr Systems and methods for maintaining synchronicity during signal transmission
US7523319B2 (en) * 2005-11-16 2009-04-21 Lenovo (Singapore) Pte. Ltd. System and method for tracking changed LBAs on disk drive

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3840862A (en) * 1973-09-27 1974-10-08 Honeywell Inf Systems Status indicator apparatus for tag directory in associative stores
US3896419A (en) * 1974-01-17 1975-07-22 Honeywell Inf Systems Cache memory store in a processor of a data processing system
FR2315744A1 (fr) * 1975-06-27 1977-01-21 Telemecanique Electrique Dispositif auxiliaire d'adressage virtuel
US3976865A (en) * 1975-08-15 1976-08-24 International Business Machines Corporation Error detector for an associative directory or translator
US4084236A (en) * 1977-02-18 1978-04-11 Honeywell Information Systems Inc. Error detection and correction capability for a memory system
US4357656A (en) * 1977-12-09 1982-11-02 Digital Equipment Corporation Method and apparatus for disabling and diagnosing cache memory storage locations
US4190885A (en) * 1977-12-22 1980-02-26 Honeywell Information Systems Inc. Out of store indicator for a cache store in test mode
US4197580A (en) * 1978-06-08 1980-04-08 Bell Telephone Laboratories, Incorporated Data processing system including a cache memory
US4225922A (en) * 1978-12-11 1980-09-30 Honeywell Information Systems Inc. Command queue apparatus included within a cache unit for facilitating command sequencing
US4490782A (en) * 1981-06-05 1984-12-25 International Business Machines Corporation I/O Storage controller cache system with prefetch determined by requested record's position within data block
US4476526A (en) * 1981-11-27 1984-10-09 Storage Technology Corporation Cache buffered memory subsystem

Also Published As

Publication number Publication date
JPH0337218B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1991-06-04
US4637024A (en) 1987-01-13
EP0180821B1 (en) 1992-03-04
DE3585496D1 (de) 1992-04-09
EP0180821A2 (en) 1986-05-14
EP0180821A3 (en) 1988-08-10
JPS61114356A (ja) 1986-06-02

Similar Documents

Publication Publication Date Title
CA1228674A (en) Redundant page identification for a catalogued memory
EP0113240B1 (en) Virtual memory address translation mechanism with controlled data persistence
US6304992B1 (en) Technique for correcting single-bit errors in caches with sub-block parity bits
US6192487B1 (en) Method and system for remapping physical memory
US4680700A (en) Virtual memory address translation mechanism with combined hash address table and inverted page table
EP0407119B1 (en) Apparatus and method for reading, writing and refreshing memory with direct virtual or physical access
US6035432A (en) System for remapping defective memory bit sets
US5371870A (en) Stream buffer memory having a multiple-entry address history buffer for detecting sequential reads to initiate prefetching
US6480975B1 (en) ECC mechanism for set associative cache array
US3800294A (en) System for improving the reliability of systems using dirty memories
JP3987577B2 (ja) システム管理モード情報を他の情報と共にキャッシュに入れる方法および装置
EP0009412A2 (en) Block replacement in a high speed cache memory system
JPH0526217B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
US4371963A (en) Method and apparatus for detecting and correcting errors in a memory
JPH0524540B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
US5357521A (en) Address sensitive memory testing
US5287482A (en) Input/output cache
US4896257A (en) Computer system having virtual memory configuration with second computer for virtual addressing with translation error processing
US6772289B1 (en) Methods and apparatus for managing cached CRC values in a storage controller
US5544293A (en) Buffer storage system and method using page designating address and intra-page address and detecting valid data
JPS6129024B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP0150522A2 (en) Data processing system with hierarchical memory protection
JPS59207098A (ja) 情報処理装置
JPH01194046A (ja) メモリアクセス方式
CA1220286A (en) Virtual memory address translation mechanism with combined hash address table and inverted page table

Legal Events

Date Code Title Description
MKEX Expiry