CA1163378A - Underpass in a semiconductor device - Google Patents

Underpass in a semiconductor device

Info

Publication number
CA1163378A
CA1163378A CA000380108A CA380108A CA1163378A CA 1163378 A CA1163378 A CA 1163378A CA 000380108 A CA000380108 A CA 000380108A CA 380108 A CA380108 A CA 380108A CA 1163378 A CA1163378 A CA 1163378A
Authority
CA
Canada
Prior art keywords
layer
oxidation
field effect
oxide
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000380108A
Other languages
English (en)
French (fr)
Inventor
Pieter J.W. Jochems
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Application granted granted Critical
Publication of CA1163378A publication Critical patent/CA1163378A/en
Expired legal-status Critical Current

Links

Classifications

    • H10P76/40—
    • H10P14/61—
    • H10W10/0126—
    • H10W10/13—
    • H10W20/20—

Landscapes

  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Local Oxidation Of Silicon (AREA)
CA000380108A 1980-06-23 1981-06-18 Underpass in a semiconductor device Expired CA1163378A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL8003612 1980-06-23
NL8003612A NL8003612A (nl) 1980-06-23 1980-06-23 Werkwijze ter vervaardiging van een halfgeleider- inrichting en halfgeleiderinrichting vervaardigd door toepassing van deze werkwijze.

Publications (1)

Publication Number Publication Date
CA1163378A true CA1163378A (en) 1984-03-06

Family

ID=19835496

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000380108A Expired CA1163378A (en) 1980-06-23 1981-06-18 Underpass in a semiconductor device

Country Status (8)

Country Link
US (1) US4374454A (enExample)
EP (1) EP0042643B1 (enExample)
JP (1) JPS5731180A (enExample)
AU (1) AU545453B2 (enExample)
CA (1) CA1163378A (enExample)
DE (1) DE3164132D1 (enExample)
IE (1) IE51994B1 (enExample)
NL (1) NL8003612A (enExample)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4561168A (en) * 1982-11-22 1985-12-31 Siliconix Incorporated Method of making shadow isolated metal DMOS FET device
JPS62119936A (ja) * 1985-11-19 1987-06-01 Fujitsu Ltd コンプリメンタリ−ｌｓｉチツプ
GB2215124A (en) * 1988-02-16 1989-09-13 Stc Plc Integrated circuit underpasses
US5306652A (en) * 1991-12-30 1994-04-26 Texas Instruments Incorporated Lateral double diffused insulated gate field effect transistor fabrication process
EP0940851B1 (en) 1992-07-31 2005-10-05 Hughes Electronics Corporation Integrated circuit security system and method with implanted interconnections
KR0144902B1 (ko) * 1995-04-17 1998-07-01 김광호 불휘발성 메모리장치 및 그 제조방법
US5783846A (en) * 1995-09-22 1998-07-21 Hughes Electronics Corporation Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering
US5767000A (en) * 1996-06-05 1998-06-16 Advanced Micro Devices, Inc. Method of manufacturing subfield conductive layer
US5973375A (en) * 1997-06-06 1999-10-26 Hughes Electronics Corporation Camouflaged circuit structure with step implants
US6396368B1 (en) 1999-11-10 2002-05-28 Hrl Laboratories, Llc CMOS-compatible MEM switches and method of making
US7217977B2 (en) * 2004-04-19 2007-05-15 Hrl Laboratories, Llc Covert transformation of transistor properties as a circuit protection method
US6815816B1 (en) * 2000-10-25 2004-11-09 Hrl Laboratories, Llc Implanted hidden interconnections in a semiconductor device for preventing reverse engineering
US6791191B2 (en) 2001-01-24 2004-09-14 Hrl Laboratories, Llc Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations
US7294935B2 (en) * 2001-01-24 2007-11-13 Hrl Laboratories, Llc Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide
US6740942B2 (en) * 2001-06-15 2004-05-25 Hrl Laboratories, Llc. Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact
US6774413B2 (en) 2001-06-15 2004-08-10 Hrl Laboratories, Llc Integrated circuit structure with programmable connector/isolator
US6897535B2 (en) 2002-05-14 2005-05-24 Hrl Laboratories, Llc Integrated circuit with reverse engineering protection
US7049667B2 (en) 2002-09-27 2006-05-23 Hrl Laboratories, Llc Conductive channel pseudo block process and circuit to inhibit reverse engineering
US6979606B2 (en) 2002-11-22 2005-12-27 Hrl Laboratories, Llc Use of silicon block process step to camouflage a false transistor
AU2003293540A1 (en) * 2002-12-13 2004-07-09 Raytheon Company Integrated circuit modification using well implants
US6799844B2 (en) 2002-12-16 2004-10-05 Xerox Corporation High shear ball check valve device and a liquid ink image producing machine using same
JP4346322B2 (ja) * 2003-02-07 2009-10-21 株式会社ルネサステクノロジ 半導体装置
US7242063B1 (en) 2004-06-29 2007-07-10 Hrl Laboratories, Llc Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
US8168487B2 (en) * 2006-09-28 2012-05-01 Hrl Laboratories, Llc Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5528229B1 (enExample) * 1971-03-19 1980-07-26
US3751722A (en) * 1971-04-30 1973-08-07 Standard Microsyst Smc Mos integrated circuit with substrate containing selectively formed resistivity regions
US4023195A (en) * 1974-10-23 1977-05-10 Smc Microsystems Corporation MOS field-effect transistor structure with mesa-like contact and gate areas and selectively deeper junctions
NL185376C (nl) * 1976-10-25 1990-03-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting.
US4290184A (en) * 1978-03-20 1981-09-22 Texas Instruments Incorporated Method of making post-metal programmable MOS read only memory
US4268950A (en) * 1978-06-05 1981-05-26 Texas Instruments Incorporated Post-metal ion implant programmable MOS read only memory
IT1166587B (it) * 1979-01-22 1987-05-05 Ates Componenti Elettron Processo per la fabbricazione di transistori mos complementari ad alta integrazione per tensioni elevate

Also Published As

Publication number Publication date
JPS622708B2 (enExample) 1987-01-21
IE51994B1 (en) 1987-05-13
DE3164132D1 (en) 1984-07-19
EP0042643B1 (en) 1984-06-13
AU545453B2 (en) 1985-07-18
IE811379L (en) 1981-12-23
NL8003612A (nl) 1982-01-18
AU7203181A (en) 1982-01-07
US4374454A (en) 1983-02-22
EP0042643A1 (en) 1981-12-30
JPS5731180A (en) 1982-02-19

Similar Documents

Publication Publication Date Title
CA1163378A (en) Underpass in a semiconductor device
CA1075372A (en) Semiconductor device with underpass interconnection zone
CA1216075A (en) Wafer fabrication by implanting through protective layer
US5424572A (en) Spacer formation in a semiconductor structure
US4078947A (en) Method for forming a narrow channel length MOS field effect transistor
US4433468A (en) Method for making semiconductor device having improved thermal stress characteristics
US4422885A (en) Polysilicon-doped-first CMOS process
EP0083816B1 (en) Semiconductor device having an interconnection pattern
US4512073A (en) Method of forming self-aligned contact openings
US4891328A (en) Method of manufacturing field effect transistors and lateral bipolar transistors on the same substrate
KR20010021740A (ko) 무선 주파수에서 사용되는 집적 회로 소자를 제조하는 방법
US4261763A (en) Fabrication of integrated circuits employing only ion implantation for all dopant layers
EP0243622B1 (en) Shallow junction complementary vertical bipolar transistor pair
US5554554A (en) Process for fabricating two loads having different resistance levels in a common layer of polysilicon
US4689872A (en) Method of manufacturing a semiconductor device
JPS6028134B2 (ja) 半導体構造体の形成方法
KR100222116B1 (ko) 자기정합된 플레이너 모놀리딕 집적회로의 종적 트랜지스터 프로세스
US4045249A (en) Oxide film isolation process
GB2156583A (en) Process for producing semiconductor device
US4472873A (en) Method for forming submicron bipolar transistors without epitaxial growth and the resulting structure
EP0051534B1 (en) A method of fabricating a self-aligned integrated circuit structure using differential oxide growth
US6313001B1 (en) Method for semiconductor manufacturing
EP0029552A2 (en) Method for producing a semiconductor device
CA1216966A (en) Method of manufacturing a semiconductor device and semiconductor device manufactured by the method
EP0337823A2 (en) MOS field effect transistor having high breakdown voltage

Legal Events

Date Code Title Description
MKEX Expiry