CA1121015A - Computer system - Google Patents
Computer systemInfo
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- CA1121015A CA1121015A CA000311503A CA311503A CA1121015A CA 1121015 A CA1121015 A CA 1121015A CA 000311503 A CA000311503 A CA 000311503A CA 311503 A CA311503 A CA 311503A CA 1121015 A CA1121015 A CA 1121015A
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- bus
- switch
- computer
- input
- switches
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
Abstract
S P E C I F I C A T I O N
TO ALL WHOM IT MAY CONCERN:
BE IT KNOWN that I, RUDOLF KOBER, a citizen of Germany, residing at Rattenberger Strasse 30, 8000 Muenchen 70, Germany, have invented certain new and useful improvements in "A COMPUTER SYSTEM "
and I do hereby declare that the following is a full, clear and exact description of the same, reference being had to the accompanying sheets of drawing and to the numerals of reference marked thereon which form a part of this specification.
ABSTRACT OF THE DISCLOSURE
A computer system includes a number of individual computers which can be coupled to a control computer by way of a system bus which comprises at least two bus systems, in particular an address and control bus and at least one data bus. The system bus is divided into sections by one or more bus switches and each bus switch operates such that the two bus systems can be interrupted under its control, its flow-through direction can be separately switched over for each of the bus systems and it can be directly addressed by a control computer and at least one data exchange computer is connected to the system bus at various points.
TO ALL WHOM IT MAY CONCERN:
BE IT KNOWN that I, RUDOLF KOBER, a citizen of Germany, residing at Rattenberger Strasse 30, 8000 Muenchen 70, Germany, have invented certain new and useful improvements in "A COMPUTER SYSTEM "
and I do hereby declare that the following is a full, clear and exact description of the same, reference being had to the accompanying sheets of drawing and to the numerals of reference marked thereon which form a part of this specification.
ABSTRACT OF THE DISCLOSURE
A computer system includes a number of individual computers which can be coupled to a control computer by way of a system bus which comprises at least two bus systems, in particular an address and control bus and at least one data bus. The system bus is divided into sections by one or more bus switches and each bus switch operates such that the two bus systems can be interrupted under its control, its flow-through direction can be separately switched over for each of the bus systems and it can be directly addressed by a control computer and at least one data exchange computer is connected to the system bus at various points.
Description
~L~Jo~
BACKGROUND OF THE INVENTION
_ ,., _., - -Field of the Invention _, . ....
The present invention relates to a computer system wherein anumber of individual computers can be coupled to a control computer by way of a system bus which comprises at least two bus systems including an address and control bus and at least one data bus.
Description o~ the Prior ~rt A computer system of the type generally described above is known from the German published application 2S 46 202. In this computer systern the control computer distributes the data by consecutively supplying the operational result of each individual computer to the system bus and recording this result in the remaining individual computers, irrespectively of how many individual computers utilize the result. l~herefore, the number of exchange cycles required for the total data exchange corresponds to the number of results which must be distributed to the individual computers.
The degree of efficiency of computer systems o~ the type mentioned above is greatly dependent upon the duration of the information exchange between the individual computers. It is therefore desirable to achieve as short as possible an exchange interval.
Many problems which must be processed involve limited vicinity coupling, i.e. *ata only requires to be exchanged between adjacent elementary func~ions. In computer systems of the type described above, this means that an exchange is only required between those individuaI computers which are arranged at a limited dis~ance from one another. Limited vicinity coupling between individual computers in a computer system is known from field computers. In this connection, one may refer to GOH.Barnes, R.M.Brovvn, M. Kato, D.J.Kuck, D.L.Slotnik, R.A. Stokes: "~he ILLIAC IV Computer'~j IEEE ~ransactions on Computers, ~ol. C-17, No. 8, August 1968, wherein the individual computers are permanently coupled to one another, e.g. each individual computer is coupled to four neighboring computers. This rigid coupling is only advantageous, however, in the case of a few problems; in the case of problems in which the coupling does not confo~n with the computer structure such as occurs, for example, in the case of couplings of higher order or irregular coupling, the rigidity complicates and slows down the data exchange to a considerable extent giving rise to long exchange durations.
SllMMARY OF THE INVENTION
~ he primary object of the present invention is to provide a computer system of the type mentioned above wherein the limited vicinity coupling can be exploi~ed in order to achieve a reduction in the exchaoge phase.
This o~ject is achieved in that the system hus is divided into sections by means of one or more bus switches and tha~ each bus switch possesses the following characteristics:
(a3 the two bus systems can be interrupted under its control;
(b) its flow-through direction can be separately switched over for each of the bus systems; and (c) it can be directly addressed by the control computer, and that at least one data exchange computer is connected to the system bus at different points.
In the case of problems involving heavy or irregular coupling, this computer system allows all of the bus switches to be closed and the results to be exchanged between all of the individual compuLers.
In the case of problems involving limited vicinit~r coupling, by o~ening bus switches it is possible to divide the system into a plurality of sections within which the data exchange can take place simultaneously and independently in each case under the control o~ a data exchange cornputer .
As a result of this parallel exchange of data, the exchange phase can be considerably shortened in the case of man~r problems.
An advantageous embodiment o~ the invention is constructed such that a bus switch is arranged hetween two adjacent points at which an individual computer can be connected to the sys~em bus.
Another advantageous embodiment of the inventio~ provides that a data exchange computer is connected to every second connection point .
An advantageous further feature of the invention is that in a system one or more groups which each comprise two or more adjacent bus switches can be bridged by a further bus switch, and that each further bus switch possesses the following characteristics:
(a) its flow-through direction can be switched over;
~ b~ the switch is enabled when all the switches within the group which it bridges are enabled and simultaneously interrupts a switch within the group located at one end; and ~ (c) it interrupts when at least one of the other switches within the group is i~terrupted.
A computer system constructed in accordance with the present inYention is advantageously further developed in such a manner that a multi-stage bridging system is formed so that in each stage, with the exception of the highest stage, one or more than one group, each of whîch comprises two or more further bus switches, can be bridged by a further bus switch of the next higher stage, where the lowest stage comprises the further bus switches by which the bus switches on the system bus can be bridged, and that each further bus switch which bridges a group of ~ur~her bus switches possesses the following characteristics:
i~
(a) its flow-through direction can be switched over;
(b) the switch is enabLed when all of the switches within the group which it bridges are enabled and simultaneously interrupts a switch within the gralp located at one end; and (c) it interrupts when at least one ~ the other switches within the group is interrupted.
a~
3~
According to a broad aspect of the invention, there is provided, in a computer system o~ the type in which a plurality of individual computers are operatively connected to a control computer by way of at least two bus systems including an address and control bus and at least one data bus, the improvement therein comprising at least one bus switch connected in and operable to interrupt said bus systems into sections, including means for controlling the flow-through direction separately for each of the bus systems, at least one data exchange computer and means for connecting the data exchange computer into the bus system at a point along the bus systems.
-4a-is BRIEF DESCRIPTION OF IHE DRAWIl~GS
Other objerts, features and advantages of the invention, its organization, construction and mode of operation will be best under-stood from the following detailed description, taken in conjunction with the accompanying drawings, on which: :
~ IG. 1 is a block diagram of the construction of the computer system;
FIG. 2 is a block diagram of a two-stage bridging system;
FIG. 3 is a two-dimensional grid network;
FIG. 4 illustrates a linear diaLgram;
FIG. 5 is a block diagram which illustrates an exemplary embodiment of a bus switch and o~ a further bus switch;
FIG. 6 is a block diagram illustration of the construction of a two-path ~us driver;
FIG. 7 is a schematic logic diagram of the construction of the control logic of the bus switch illustrated in FIGo 5;
FIG. 8 is a block diagram illustration of the construction of the selection logic for the bus switch illustrated in FIG. 5;
FIG. 9 is a logic circuit diagram of the construction of the release logic for the bus switch illustrated in FIG. 5;
g~s FIG. 10 is a block system diagram illustrating the design of a bridging of a group of switches and fur~her bus switches by a further bus switch;
FIG~ 11 illus~rates two data flow diagrams for a bridging operation;
FIG. 12 is a schematic block diagram which illustrates an exemplary embodiment of the interconnection of the adjacent bus switches;
FIG. 13 is a block diagram illustrating an exemplary em~odiment of the principle of directional swi~ch-over; and FIG. 14 is a data flow diagram relating to the two-stage bridging system illustrated in FIG. 2.
:;
DESCRIPTION OF THE PREFERRED EMBODIMENTS
- Referring to FIG. 1, a p~urality of individual computers Ml--M6 are connected to a system bus 1 at respective points ml--m6.
Between two adjacent conneotion points mi and mi+l, a bus switch S
is arranged în the system bus. There are, accordingly, five bus switches Sl--S5 available in this particular system. The bus switches serve to dhride the system bus into sections al--a6. At the points m2, m4 and m6 of the system bus, a data exchange computer ATRl, ATR~2 and ATR3 is respectively connected. On the left-hand side of the system bus a control computer STR is connected. The system can be imagined to continue on the right-hand side. Prefera~ly, a computer system of this type is constructed by means of micro-pr~essor modules.
FIG. 2 schematically illustrates a two-stage bridging system.
The bus switches S6--S20 are arranged on a system bus 2. The bus switches S9--Sll can be bridged by a further bus switch S~21, the bus switches S12--S14 can be bridged by a further bus switch S22, and the bus switches S15--S17 can be bridged by a further bus switch S23 .
Here che further bus switches S21--S23 forrn the first stage of the bridging system. These bus switches, in turn, can be bridged by a further bus switch S24 which forms the second stage of the b:ridging system. Each of the further bus switches must be able to fulfill the following functions:
its flow-through direction must be able to be swltched over;
it must be enabled when all of the bus switches or further bus switches in the next lower stage which it serves to bridge are them-selves enabled and must simultaneously interrupt a switch within this g~oup located at :one end; and it must interrupt when at least one of the other switches within this g~up is interrupted.
Before a specific example of a computer system of the type illustrated in FIG~. 1 or 2 will be discussed in detail, reference will be tak~n to FIGS. 3 and 4 to illustrate how, in the described computer structure, the exchange width can be matched to the coupling width of the problem to be handled. Hereg the influence of the coupling method upon the duratior~ of the data exchange will be investigated in the form of an example. ~he example considered will be a two-dimensional problem structure such as illustrated in FIG. 3. Structures of this kind occur in the solution of partial differential equations in accordance with a method of finite differences which is used, for example, in field calculations or in weather forecasting. Here, data exchange is only requi.red between directly adjacent grid network points. In FIG. 3 this has been emphasized in the example of the network point i, which exchanges data only with its four closest neighbors i- 1, i - n, i + 1 and i ~ n. This problem can be represented in the given linear computer structure, for e~ample, as illustrated in FIGS. 1 or 2, in which each individual computer deals with one grid network point, in such a manner that data exchange is only required within a specific bandwidth. The individual computer which is assigned to the grid network point i must distribute its results between the individual co~nputers assigned to the points i - n, i - 1, i + 1 and i ~ n. Therefore, the band width amounts to 2n + 1.
These facts projected onto a single dimension are illustrated in FIG.
4.
The proposed computer system can be advantageously adapted to this problem by dividing the system bus into sections o~ the length 2n f 1. The bus switches effect this division. The result of the particular middle individual computer is distributed within these sections.
As a next stage, the sections of the syster.n bus are displaced by one bus switch and the results of the individual computers now located in the center of the sections are distributed, and so on. As exchange takes place simultaneously in all sections, only two n-~l exchange steps are required in order to distribute n results. As a result, the data exchange phase is reduced by a factor which is equal to the ratio of the number of grid network points/bandwidth. In the case of a two-dimensional problem where n- 100, which corresponds to a n~unber of grid points of 10 and a bandwidth o~ 201, the number of exchange steps is reduced by approximately 1/50 of the number of grid network points. Here, it must be expressly pointed out that the proposed computer system is not limited to this example, but can be advantageously adapted to other problem structures. The basis for this resides in the aforementioned characteristics which the bus switches must possess.
Referring to FIG. 5, a particularly advantageous embodiment of a bus swi~ch is illustrated. This embodiment is designed to be such that it can be used simultaneously as a further bus switch.
According to FIG. 5, the bus switch comprises a selection logic SSL, a release logic SEL, two two-path bus drivers BDl and BD2, connec~ed to the system bus, with associated control logics BC1 and BC2, where the bus driver BDl is connected into the data bus and the bus driver BD2 is connected into the address bus, and further comprises an ~perating mode transfer switch S. With the aid of the operating mode transfer switch S it is possible to switch between two operating modes, in one of which, which here is referenced A, the bus switch state is detennined by che release logic SEL, and therefore is addressed and controlled by the control computer. In the other operating mode, wl~ich here has been referenced B, the operating state is established via an ENABLE input which can be connected to a ENABLED-output of another bus switch constructed in a similar manner, as a result of which tkebus switch can adopt the operating state of the other.
When the bus switch is employed as a further bus switch in a s~age of a one-stage or multi-stage bridging system, the ENABLED ou~puts of the bridged switches in the next lower stage are connected by way of an AND gate to the ENABLE input of this further bus switch, as a result of which the cnaracteristics mentioned above are achieved in the latter, namely, the switch, the switch is enabled when all of the switches within the group which lt bridges are enabled and simultaneously interrupts a switch wilthin the group Iocated at one end, and it interrupts when at least one of the other switches within the group is interrupted. Between the ENABLED output and the operating mode transfer switch S there is also connected a driver 50 having an open collector output, which facili~ates a wired AND logic link between the ENABLED outputs of a plurality of bus switches.
FIG. 6 illustrates the construc~ion of the two bidirectional bus drivers FsD1 and BD2 which are of identical construction. This is a bus driver for bit-parallel transmission of a byte which is composed of two four-bit-parallel two-path bus drivers SAB 8216 (see detailed description in Mikro-processor-Bausteine "I)atenbuch" 1976/77, System SAB 8080 by Siemens ~G, Bereich Bauelemen~e, Balanstrasse 73, 8000 Muenchen 80). Here, and in the following, the inputs and outputs of the modules will be provided with the references given in the above-mentioned publication. By way of the inputs CS of the two modules which are connected to a common input cs, ~he bus driver can be blocked. ~he direction of the data flow is determined by way of the inputs DIEN which are linked to a common input dien of the bus driver. Further details are provided in the above-mentioned publication.
~he terminals DI, DO and ~ act as substitutes for the inputs DIo--DI3, DOo~~DO3 and DBo--DB3 given therein.
FIG. 7 is a detailed illustration of the construction of the control logic BCl and BC~2. The module 7408 is suitable for the three AND gates ADl, AD2 and AD3 each of which has two inputs, the module 7427 is suitable for the NOR gates, the module 7404 is suitable for the inverters 85 and 86, and the modules 7422 having an open collector is suitable for the N~NI~ gate 87 which has three inputs, all produced by Siemens AG (see "Digitale Schaltungen", Datenbuch 1976/77 of Siemens AG, published by Bereich Bauelemente, ~Tertrieb, 8000 Muenchen 80, Balanstrasse 73). The direction of the input DIR C~RL
1 and DIR CTRL 2 can be determined by way of the input DIR Cll~L
INl to which it is connected. This input is connected, on the one hand, by way of the inverter 85 to an input of both the NAND gate 87 and the AND gate 81 and, on the other hand, is directly connected to an input of the AND gate 83. In addition, a direct connection exists between the aforementioned input and the output 702 which is connected to the input dLen of the associated two-path bus driver. The input enable 1 and enable 2 is connected, on the one hand, to the output 53 OI the operating mode transfer switch S and, Oll the other hand, to the second input of the AND gate 83 and to a second input of the gate 87 and to an input of the NOR gate 84. The main function of the input enable 1 is, by way of the output 701 which must be connected on the one hand to the output of the NOR gate 84 and on the other hand to the input cs of the two-path bus driver BDl and BD2, to block or release the latter. When the relevant bus driver is released, via the input enable 1 or enable 2 of the control logic, the directional information can be forwarded tO the next bus switch. This information is input into the bus switch via the inputs DIR CTRL IN1 and DIR
Cl~L IN2 (see FIG. 5). An input DISL of the control logic is connected to the second input of the AND gate 81, whereas the input DISR1 and DISR2 is connected to an input of the AND gate 82. The output of each of these AND gates is connec~ed to a second and third input of the NOR gate 84. The one input of the AND gate 82 is connected by way of an inverter 86 to the third input of a NAND gate 87, and the second input of the AND gate 82 is connected to the first input of the NAND gate 87. The bus drivers BD1 and BD2 can be selectively blocked for a right-hancl or left-hand data flow direction via the inputs DISR1 and DISR2. The output ~ the AND gate 83 forrns the ou~ut DISR OUTl and DISR OUT2 of ~he bus switch. The latter output is required in a one-stage or multi-stage bridging system. The output of the NOR gate 87 forms the output DIR Cll~L OUTl and DIR CTRL OUT2 o~ the bus switch.
FIG. 8 is a detailed illustration of the switch selection logic SSL. The switch selection logic comprises two four-bit comparators 81 and 82 arranged next to one anoth~?r, such as the module 7485 in '~igitale Schaltungen", supra, Pages 122 and 123. The inputs 2 (A ~ B), 3 (~ = B) and 4 (A > B) of the comparator 82, as referenced in the above-mentioned publication, are connected in parallel with the corresponding outputs 7 (A < B), 6 (A = B) and 5 (A ~ B) of the comparator 81. The four-bit terrninals A and B are identical to the terminals Ao--A3 and B --B in the publication. The terminals ~ of the two comparators 81 and 82 together form a byte terminal which must be connected to the address bus. The four-bit terrninals B of the two comparators are connected in parallel to an eight-times coder switch having a pull-up resistor. The input 3 (A = B) o~ the comparator 81 is connected via a resistor 84 to the supply voltage which corresponds to the binary logic vaiue "1", whereas the output 6 (A = B) of the comparator 82 is connected to the /'selected" input of the release logic SEL. With the coder switch 83 schematically illustrated in FIG. 8, the bus switch can be provided with a fixed switch number. If the address input via the inputs A
agrees with the switch number, the output 6 (A = B) is connected to a logic "1 ".
FIG. 9 illustrates the release logic SEL in detail. rhis circuit contains four OR gates 91--94 each having two inputs, two AND gates 95 and 96 each having ~hree inputs, a D-flip-flop 97 and an inverter 98. The "selected" input is connected by way of the inverter 98 to an output of the OR gate 91. The output of the OR
gate 91 is connected, on the one hand, to an input of the AND gate 95 and to an input of the AND gate 96. The output of the AND gate 95 is connected to the input D, and the ou~put of the AND gate 96 is connected to the input T of the D-flip-flop 97 (for example the module 7474 in the aforementionecl publication "Digitale Schaltungen's, ~ages 190 and 191, the inputs and outputs referenced as therein~. The in~ut R of the flip-flop 97 is connected to the RESET input of ~he bus switch. The input S of the flip-flop is continuously connected to a logic "1". The output Q of the flip-flop 97 is corLnected to an input of the OR gate 94, to the outputs EN RIGHT OUT and EN LEFT OUT
of the bus switch (see FIG. 5). The output of the OR gate 94 forrns the enabled output of the release logic which is connecte(l to the input 51 of the operating mode transfer switch S whose other input 52 is connected to the input ENABLE of the bus switch. ~e input SHIFT RIGHT of the bus switch is connected, on the one hand, ~o a second input of the AND gate 96 and to an input of the OR gate 93.
Similarly, the input SH-IFT LEFT of the bus switch is connected to the third input of the AND gate 96 and to an input ~ the OF~ gate 92.
The input ~ELECTION MODE is connected to the second input of the OR gate 94, whereas the input SELECT STB is connected tO the second input of the OR gate 91, and the input EN LEFT IN is connected to the second input of the OR gate 92. The output of the OR gate 92 is connec~ed to a second input and the output of the OR
gate 93 to the third input of the AND gate 95. The D-flip-flop 97 which serves as a marker flip-flop can be set by ~hree different - ~4 -signals:
If the bus switch is selected (selected "1"), with a pulse marking flip-flop is set at a logic "0", i.e. the ou:put Q is connected to "0";
With a ~F~FT~ pulse, the flip-flop is loaded wi~h the state of the input EN LEFT IN; and With a SHIFT RIGHT pulse, is loaded with the state of the input SHIFT RIGHT IN which is connected to the second input of the OR gate 93.
The advantageous circuit comprising SHIFT LEFT and SHIFT RIGHT
which has been described is intended to facilitate a simple shift of bus sections which have already been divided by connecting a SHIFT LEFT
or SHI~T RIGHT pulse~ as a result of which the computer system can be particularly advantageously ennplosred for problem structures such as described in FIGS. 3 and 4.
When the SELECTION MODE input is connected to a logic "0" the relevant binary value present at the output Q of the flip-flop is conn~l~ted to the enabled output. The bus switch now interrupts when the enabled output carries "0". Otherwise it is open. If the SELECTION ~ODE input is connected to a logic "1" enable likewise carries this value~ which rneans that the bus switch is closed. In ~is manner it is possible to switch over be~ween a system bus divided into sections and a through-going system bus without any loss of time.
The marking flip-flop can be reset to ~he basic positlon Q = "1" by way of the ~ input. The function of the marking flip-flop is to "mark" the bus switches which are to interrupt in the case of the "selection mode'~ operating mode. As described above9 this marking can be carried out in three different ways. The bus switch remains closed, however, if a "1" is present at the SELECTION MODE input.
As a result, items of information can be t:ransmitted from the control computer to all of the computers, data exchange computers and bus switches provided in the system. As a result9 the sequence of marking of the bus switches is arbitrary. ~, on the other hand, the bus switch were to interrupt immediately, all the components located behind the switch would be unable to be approached by the control computer. It would therefore be necessary to first interrupt the more remote bus switches. If the input SELE`C~FON MODE- is connected to a "O", the system bus is interruptecl at the marked points.
During a data exchange with a divided system bus, a temporary and shor~-term necessity can consist in gainmg access from the control computer to all or a few ~ the more remote components, for example in order to modify the programs in the data e~change computers. For this pu~pose, the time saving transfer ~etween divided and through-connected system bus configuration i~ provided which can be achieved in a very simple manner with the aid of the flip-flQp .
FIG. 10 illus~rates a bridging of four bus switches S10l--Sl04 by a further bus switch S201. Each of the switches is constructed as illustrated in FIG. 5. The ENABLED outputs of the four bus switches are connected via a wired AND circuit to the ENABLE input of the further bus switch and to the DISL input of the bus switch S101. The outputs DISR1 OUT and DISR2 OUT of the further bus switch are connected to the corresponding inputs DISR1 and DISR2 of the bus switch S104. In the case of all the other bus switches and the further bus switch, these inputs are connected to ground. ~part from the bus switch S101, in the case of the further bus switch and all the other bus switches, the inputs ~ISL are likewise connec~ed to ground.
The inputs DIR CTRLl and DIR CTRL2 are connected to the con~rol computer via control lines DIR CTRLl+ 2. All the other inputs and outputs of the bus switches are likewise connected to the control computer ~ia a control bus SWITCH CONl~OL BtJS. The mode of operation of this connection is such that when all the bus swi~ches are released, and the further bus switch is likewise released, simultaneously, via the inputs DISL, the left-hand bus switch S101 is blocked in respect of the left-hand data flow direction and via the inputs DISR1 and DISRZ the right-hand bus switch S101 is blocked in respect of right-hand directions. (An exception is formed ~y the bridging of arms with data sources which will be described later in this description.) In this manner, the data paths 101 and 112 illustrated in FIG. 11 are formed.
The illustrated bridging can be used for any bridging stage.
This means that the switches S101--S104 can equally constitute further bus switches of the first or a higher stage o~ a bridging system. In this manner it is possible to construct any multi-stage bridging system.
~ z~
In FIG. 12, a zone 120 framed in broken lines in FIG. 10 has been illustrated in full detail.
Here the inputs and ou~uts whose use is dependent upon the setting of the switch are marked with an asterisk. When the switch is used as a bus switch in a system without bridgings, all three inpu~s DISR1, DISRZ and DISL are connected to ground. With bridgings, the interconnectian of the four upper outputs can be gathered from FIG.
10. The sarne applies when the switch S102 is a left-hand end switch and the switch S103 is a right-hand end switch. The wiring o~ the other inputs ancl outputs o~ the two switches, therefore the switches which are not marked with an asterisk, is obvious from FIG. 12.
FIG. 13 illustrates four bus switches S121--S124 on a data bus 125 OI a cornputer system. The directional transfer is to be explained on the basis of this drawing. Between two adjacent bus switches, an individual computer or data exchange computer i~
connected as the source Q1--Q3 f information to the data bus. The construction of the bus switches is as illustrated in FIGo 5~ with the difference th~t the selection logic BC1 and BC2 is replaced by a simplified, extra logic in each case pr~vided with a driver and a resistor. The function of this simplified logic is identical to that illu~trated in FIG. 7, when the inputs DISR1 and DISR2, DISL, DIR
CTRL IN 1 and DIR CTRL IN 2 are connected to a logic "0" and enable 1 and enable 2 are connected to "1". In FIG. 13 the input dien o~ the bus driver BD1 of each bus switch is connected to a , control line ~:)IR CTRL. Between two adjacent connection points, a driver having an open collector output is arranged in the control line, and furthermore each of these sections can be connected by way of a resistor to the supply voltage. The drivers are provided with the references 131--134 and the resistors with the references 135--138.
Each source has an output q1~ q2 or q3 which is connected to the control line DIR CTRL. This output is connected to a logic "O" when the source is ~ransmitting, i.e. when the individual computer or exchange computer is emitting data. An arrangement which is of identical construction and which is provided with a control line to which sources are connected can be additionally provided for the inputs dien of the two-path bus driver BD2.
The arrangement illustrated in FIG. 13 realizes the principle of directional transfer. This is based upon the ~ollowing considerations:
In each bus section, there is only one transmitting source for each bus system in each exchange c~rcle.
In the case of the control and address bus this can be the control computer or an exchange computer and in the case of the data bus can consist of a specific individual computer. This source transmits information to the remaining elements OI the bus section;
this means that the bus drivers must be connected in the direction leading away from the source.
The principle of directional transfer is identical for both bus systems; therefore, only the data bus system has been illustrated in FIG. 13. In FIG. 13 the bus driver direction is controlled via the control line DIR CTRL. If no source is transmitting, it is colmected to a logic "1", which is effected by the resistors. As a result, the drivers are connected to the right-hand direction. If a source now wishes to transmit information, it connects a logic "0" to the associated sec~ion of the control line. This value is communicated to the drivers arranged on the left-hand of the source and consequently these drivers reverse their direction to the left. As a result, the source can emit its information in a radiating fashion.
In the case of bridged arms of a bridging system, the source must connect such control lines DIR CTRL of the further bus switches in the same way to a logic "0". In FIG. 14, the data flow in the case oî sources wi~hin bridged sections of a bxidging system corresponding to FIG. 2 has been represented by way of example.
The items of information emitted fro~ the source are forwarded tO a bridged section of the next higher stage via the extreme right bus switch of the bridged section to which the source is connec~ed. The same then applies to the forwarding from stage to stageO Therefore, in this case for each stage the extreme rlght bus driver of a section which receives information from the next lower stage is not blocked for the right-hand data flow direction, even when all the bus switches in this section are released. The output DISR OIJT of the bridging bus switch is inactive because its data flow direction is toward the left .
112:1LO15 Finally, the function of the data excbange computer will be described. When the system bus has been divided into sections, these sections represent independent computer systems and require a "central" cornputer which under~akes the distribution of the results within the independent section. In this case i~ must fulfill the two following functions:
(1) Switching of a data path upon which data is to be transmitted; and
BACKGROUND OF THE INVENTION
_ ,., _., - -Field of the Invention _, . ....
The present invention relates to a computer system wherein anumber of individual computers can be coupled to a control computer by way of a system bus which comprises at least two bus systems including an address and control bus and at least one data bus.
Description o~ the Prior ~rt A computer system of the type generally described above is known from the German published application 2S 46 202. In this computer systern the control computer distributes the data by consecutively supplying the operational result of each individual computer to the system bus and recording this result in the remaining individual computers, irrespectively of how many individual computers utilize the result. l~herefore, the number of exchange cycles required for the total data exchange corresponds to the number of results which must be distributed to the individual computers.
The degree of efficiency of computer systems o~ the type mentioned above is greatly dependent upon the duration of the information exchange between the individual computers. It is therefore desirable to achieve as short as possible an exchange interval.
Many problems which must be processed involve limited vicinity coupling, i.e. *ata only requires to be exchanged between adjacent elementary func~ions. In computer systems of the type described above, this means that an exchange is only required between those individuaI computers which are arranged at a limited dis~ance from one another. Limited vicinity coupling between individual computers in a computer system is known from field computers. In this connection, one may refer to GOH.Barnes, R.M.Brovvn, M. Kato, D.J.Kuck, D.L.Slotnik, R.A. Stokes: "~he ILLIAC IV Computer'~j IEEE ~ransactions on Computers, ~ol. C-17, No. 8, August 1968, wherein the individual computers are permanently coupled to one another, e.g. each individual computer is coupled to four neighboring computers. This rigid coupling is only advantageous, however, in the case of a few problems; in the case of problems in which the coupling does not confo~n with the computer structure such as occurs, for example, in the case of couplings of higher order or irregular coupling, the rigidity complicates and slows down the data exchange to a considerable extent giving rise to long exchange durations.
SllMMARY OF THE INVENTION
~ he primary object of the present invention is to provide a computer system of the type mentioned above wherein the limited vicinity coupling can be exploi~ed in order to achieve a reduction in the exchaoge phase.
This o~ject is achieved in that the system hus is divided into sections by means of one or more bus switches and tha~ each bus switch possesses the following characteristics:
(a3 the two bus systems can be interrupted under its control;
(b) its flow-through direction can be separately switched over for each of the bus systems; and (c) it can be directly addressed by the control computer, and that at least one data exchange computer is connected to the system bus at different points.
In the case of problems involving heavy or irregular coupling, this computer system allows all of the bus switches to be closed and the results to be exchanged between all of the individual compuLers.
In the case of problems involving limited vicinit~r coupling, by o~ening bus switches it is possible to divide the system into a plurality of sections within which the data exchange can take place simultaneously and independently in each case under the control o~ a data exchange cornputer .
As a result of this parallel exchange of data, the exchange phase can be considerably shortened in the case of man~r problems.
An advantageous embodiment o~ the invention is constructed such that a bus switch is arranged hetween two adjacent points at which an individual computer can be connected to the sys~em bus.
Another advantageous embodiment of the inventio~ provides that a data exchange computer is connected to every second connection point .
An advantageous further feature of the invention is that in a system one or more groups which each comprise two or more adjacent bus switches can be bridged by a further bus switch, and that each further bus switch possesses the following characteristics:
(a) its flow-through direction can be switched over;
~ b~ the switch is enabled when all the switches within the group which it bridges are enabled and simultaneously interrupts a switch within the group located at one end; and ~ (c) it interrupts when at least one of the other switches within the group is i~terrupted.
A computer system constructed in accordance with the present inYention is advantageously further developed in such a manner that a multi-stage bridging system is formed so that in each stage, with the exception of the highest stage, one or more than one group, each of whîch comprises two or more further bus switches, can be bridged by a further bus switch of the next higher stage, where the lowest stage comprises the further bus switches by which the bus switches on the system bus can be bridged, and that each further bus switch which bridges a group of ~ur~her bus switches possesses the following characteristics:
i~
(a) its flow-through direction can be switched over;
(b) the switch is enabLed when all of the switches within the group which it bridges are enabled and simultaneously interrupts a switch within the gralp located at one end; and (c) it interrupts when at least one ~ the other switches within the group is interrupted.
a~
3~
According to a broad aspect of the invention, there is provided, in a computer system o~ the type in which a plurality of individual computers are operatively connected to a control computer by way of at least two bus systems including an address and control bus and at least one data bus, the improvement therein comprising at least one bus switch connected in and operable to interrupt said bus systems into sections, including means for controlling the flow-through direction separately for each of the bus systems, at least one data exchange computer and means for connecting the data exchange computer into the bus system at a point along the bus systems.
-4a-is BRIEF DESCRIPTION OF IHE DRAWIl~GS
Other objerts, features and advantages of the invention, its organization, construction and mode of operation will be best under-stood from the following detailed description, taken in conjunction with the accompanying drawings, on which: :
~ IG. 1 is a block diagram of the construction of the computer system;
FIG. 2 is a block diagram of a two-stage bridging system;
FIG. 3 is a two-dimensional grid network;
FIG. 4 illustrates a linear diaLgram;
FIG. 5 is a block diagram which illustrates an exemplary embodiment of a bus switch and o~ a further bus switch;
FIG. 6 is a block diagram illustration of the construction of a two-path ~us driver;
FIG. 7 is a schematic logic diagram of the construction of the control logic of the bus switch illustrated in FIGo 5;
FIG. 8 is a block diagram illustration of the construction of the selection logic for the bus switch illustrated in FIG. 5;
FIG. 9 is a logic circuit diagram of the construction of the release logic for the bus switch illustrated in FIG. 5;
g~s FIG. 10 is a block system diagram illustrating the design of a bridging of a group of switches and fur~her bus switches by a further bus switch;
FIG~ 11 illus~rates two data flow diagrams for a bridging operation;
FIG. 12 is a schematic block diagram which illustrates an exemplary embodiment of the interconnection of the adjacent bus switches;
FIG. 13 is a block diagram illustrating an exemplary em~odiment of the principle of directional swi~ch-over; and FIG. 14 is a data flow diagram relating to the two-stage bridging system illustrated in FIG. 2.
:;
DESCRIPTION OF THE PREFERRED EMBODIMENTS
- Referring to FIG. 1, a p~urality of individual computers Ml--M6 are connected to a system bus 1 at respective points ml--m6.
Between two adjacent conneotion points mi and mi+l, a bus switch S
is arranged în the system bus. There are, accordingly, five bus switches Sl--S5 available in this particular system. The bus switches serve to dhride the system bus into sections al--a6. At the points m2, m4 and m6 of the system bus, a data exchange computer ATRl, ATR~2 and ATR3 is respectively connected. On the left-hand side of the system bus a control computer STR is connected. The system can be imagined to continue on the right-hand side. Prefera~ly, a computer system of this type is constructed by means of micro-pr~essor modules.
FIG. 2 schematically illustrates a two-stage bridging system.
The bus switches S6--S20 are arranged on a system bus 2. The bus switches S9--Sll can be bridged by a further bus switch S~21, the bus switches S12--S14 can be bridged by a further bus switch S22, and the bus switches S15--S17 can be bridged by a further bus switch S23 .
Here che further bus switches S21--S23 forrn the first stage of the bridging system. These bus switches, in turn, can be bridged by a further bus switch S24 which forms the second stage of the b:ridging system. Each of the further bus switches must be able to fulfill the following functions:
its flow-through direction must be able to be swltched over;
it must be enabled when all of the bus switches or further bus switches in the next lower stage which it serves to bridge are them-selves enabled and must simultaneously interrupt a switch within this g~oup located at :one end; and it must interrupt when at least one of the other switches within this g~up is interrupted.
Before a specific example of a computer system of the type illustrated in FIG~. 1 or 2 will be discussed in detail, reference will be tak~n to FIGS. 3 and 4 to illustrate how, in the described computer structure, the exchange width can be matched to the coupling width of the problem to be handled. Hereg the influence of the coupling method upon the duratior~ of the data exchange will be investigated in the form of an example. ~he example considered will be a two-dimensional problem structure such as illustrated in FIG. 3. Structures of this kind occur in the solution of partial differential equations in accordance with a method of finite differences which is used, for example, in field calculations or in weather forecasting. Here, data exchange is only requi.red between directly adjacent grid network points. In FIG. 3 this has been emphasized in the example of the network point i, which exchanges data only with its four closest neighbors i- 1, i - n, i + 1 and i ~ n. This problem can be represented in the given linear computer structure, for e~ample, as illustrated in FIGS. 1 or 2, in which each individual computer deals with one grid network point, in such a manner that data exchange is only required within a specific bandwidth. The individual computer which is assigned to the grid network point i must distribute its results between the individual co~nputers assigned to the points i - n, i - 1, i + 1 and i ~ n. Therefore, the band width amounts to 2n + 1.
These facts projected onto a single dimension are illustrated in FIG.
4.
The proposed computer system can be advantageously adapted to this problem by dividing the system bus into sections o~ the length 2n f 1. The bus switches effect this division. The result of the particular middle individual computer is distributed within these sections.
As a next stage, the sections of the syster.n bus are displaced by one bus switch and the results of the individual computers now located in the center of the sections are distributed, and so on. As exchange takes place simultaneously in all sections, only two n-~l exchange steps are required in order to distribute n results. As a result, the data exchange phase is reduced by a factor which is equal to the ratio of the number of grid network points/bandwidth. In the case of a two-dimensional problem where n- 100, which corresponds to a n~unber of grid points of 10 and a bandwidth o~ 201, the number of exchange steps is reduced by approximately 1/50 of the number of grid network points. Here, it must be expressly pointed out that the proposed computer system is not limited to this example, but can be advantageously adapted to other problem structures. The basis for this resides in the aforementioned characteristics which the bus switches must possess.
Referring to FIG. 5, a particularly advantageous embodiment of a bus swi~ch is illustrated. This embodiment is designed to be such that it can be used simultaneously as a further bus switch.
According to FIG. 5, the bus switch comprises a selection logic SSL, a release logic SEL, two two-path bus drivers BDl and BD2, connec~ed to the system bus, with associated control logics BC1 and BC2, where the bus driver BDl is connected into the data bus and the bus driver BD2 is connected into the address bus, and further comprises an ~perating mode transfer switch S. With the aid of the operating mode transfer switch S it is possible to switch between two operating modes, in one of which, which here is referenced A, the bus switch state is detennined by che release logic SEL, and therefore is addressed and controlled by the control computer. In the other operating mode, wl~ich here has been referenced B, the operating state is established via an ENABLE input which can be connected to a ENABLED-output of another bus switch constructed in a similar manner, as a result of which tkebus switch can adopt the operating state of the other.
When the bus switch is employed as a further bus switch in a s~age of a one-stage or multi-stage bridging system, the ENABLED ou~puts of the bridged switches in the next lower stage are connected by way of an AND gate to the ENABLE input of this further bus switch, as a result of which the cnaracteristics mentioned above are achieved in the latter, namely, the switch, the switch is enabled when all of the switches within the group which lt bridges are enabled and simultaneously interrupts a switch wilthin the group Iocated at one end, and it interrupts when at least one of the other switches within the group is interrupted. Between the ENABLED output and the operating mode transfer switch S there is also connected a driver 50 having an open collector output, which facili~ates a wired AND logic link between the ENABLED outputs of a plurality of bus switches.
FIG. 6 illustrates the construc~ion of the two bidirectional bus drivers FsD1 and BD2 which are of identical construction. This is a bus driver for bit-parallel transmission of a byte which is composed of two four-bit-parallel two-path bus drivers SAB 8216 (see detailed description in Mikro-processor-Bausteine "I)atenbuch" 1976/77, System SAB 8080 by Siemens ~G, Bereich Bauelemen~e, Balanstrasse 73, 8000 Muenchen 80). Here, and in the following, the inputs and outputs of the modules will be provided with the references given in the above-mentioned publication. By way of the inputs CS of the two modules which are connected to a common input cs, ~he bus driver can be blocked. ~he direction of the data flow is determined by way of the inputs DIEN which are linked to a common input dien of the bus driver. Further details are provided in the above-mentioned publication.
~he terminals DI, DO and ~ act as substitutes for the inputs DIo--DI3, DOo~~DO3 and DBo--DB3 given therein.
FIG. 7 is a detailed illustration of the construction of the control logic BCl and BC~2. The module 7408 is suitable for the three AND gates ADl, AD2 and AD3 each of which has two inputs, the module 7427 is suitable for the NOR gates, the module 7404 is suitable for the inverters 85 and 86, and the modules 7422 having an open collector is suitable for the N~NI~ gate 87 which has three inputs, all produced by Siemens AG (see "Digitale Schaltungen", Datenbuch 1976/77 of Siemens AG, published by Bereich Bauelemente, ~Tertrieb, 8000 Muenchen 80, Balanstrasse 73). The direction of the input DIR C~RL
1 and DIR CTRL 2 can be determined by way of the input DIR Cll~L
INl to which it is connected. This input is connected, on the one hand, by way of the inverter 85 to an input of both the NAND gate 87 and the AND gate 81 and, on the other hand, is directly connected to an input of the AND gate 83. In addition, a direct connection exists between the aforementioned input and the output 702 which is connected to the input dLen of the associated two-path bus driver. The input enable 1 and enable 2 is connected, on the one hand, to the output 53 OI the operating mode transfer switch S and, Oll the other hand, to the second input of the AND gate 83 and to a second input of the gate 87 and to an input of the NOR gate 84. The main function of the input enable 1 is, by way of the output 701 which must be connected on the one hand to the output of the NOR gate 84 and on the other hand to the input cs of the two-path bus driver BDl and BD2, to block or release the latter. When the relevant bus driver is released, via the input enable 1 or enable 2 of the control logic, the directional information can be forwarded tO the next bus switch. This information is input into the bus switch via the inputs DIR CTRL IN1 and DIR
Cl~L IN2 (see FIG. 5). An input DISL of the control logic is connected to the second input of the AND gate 81, whereas the input DISR1 and DISR2 is connected to an input of the AND gate 82. The output of each of these AND gates is connec~ed to a second and third input of the NOR gate 84. The one input of the AND gate 82 is connected by way of an inverter 86 to the third input of a NAND gate 87, and the second input of the AND gate 82 is connected to the first input of the NAND gate 87. The bus drivers BD1 and BD2 can be selectively blocked for a right-hancl or left-hand data flow direction via the inputs DISR1 and DISR2. The output ~ the AND gate 83 forrns the ou~ut DISR OUTl and DISR OUT2 of ~he bus switch. The latter output is required in a one-stage or multi-stage bridging system. The output of the NOR gate 87 forms the output DIR Cll~L OUTl and DIR CTRL OUT2 o~ the bus switch.
FIG. 8 is a detailed illustration of the switch selection logic SSL. The switch selection logic comprises two four-bit comparators 81 and 82 arranged next to one anoth~?r, such as the module 7485 in '~igitale Schaltungen", supra, Pages 122 and 123. The inputs 2 (A ~ B), 3 (~ = B) and 4 (A > B) of the comparator 82, as referenced in the above-mentioned publication, are connected in parallel with the corresponding outputs 7 (A < B), 6 (A = B) and 5 (A ~ B) of the comparator 81. The four-bit terrninals A and B are identical to the terminals Ao--A3 and B --B in the publication. The terminals ~ of the two comparators 81 and 82 together form a byte terminal which must be connected to the address bus. The four-bit terrninals B of the two comparators are connected in parallel to an eight-times coder switch having a pull-up resistor. The input 3 (A = B) o~ the comparator 81 is connected via a resistor 84 to the supply voltage which corresponds to the binary logic vaiue "1", whereas the output 6 (A = B) of the comparator 82 is connected to the /'selected" input of the release logic SEL. With the coder switch 83 schematically illustrated in FIG. 8, the bus switch can be provided with a fixed switch number. If the address input via the inputs A
agrees with the switch number, the output 6 (A = B) is connected to a logic "1 ".
FIG. 9 illustrates the release logic SEL in detail. rhis circuit contains four OR gates 91--94 each having two inputs, two AND gates 95 and 96 each having ~hree inputs, a D-flip-flop 97 and an inverter 98. The "selected" input is connected by way of the inverter 98 to an output of the OR gate 91. The output of the OR
gate 91 is connected, on the one hand, to an input of the AND gate 95 and to an input of the AND gate 96. The output of the AND gate 95 is connected to the input D, and the ou~put of the AND gate 96 is connected to the input T of the D-flip-flop 97 (for example the module 7474 in the aforementionecl publication "Digitale Schaltungen's, ~ages 190 and 191, the inputs and outputs referenced as therein~. The in~ut R of the flip-flop 97 is connected to the RESET input of ~he bus switch. The input S of the flip-flop is continuously connected to a logic "1". The output Q of the flip-flop 97 is corLnected to an input of the OR gate 94, to the outputs EN RIGHT OUT and EN LEFT OUT
of the bus switch (see FIG. 5). The output of the OR gate 94 forrns the enabled output of the release logic which is connecte(l to the input 51 of the operating mode transfer switch S whose other input 52 is connected to the input ENABLE of the bus switch. ~e input SHIFT RIGHT of the bus switch is connected, on the one hand, ~o a second input of the AND gate 96 and to an input of the OR gate 93.
Similarly, the input SH-IFT LEFT of the bus switch is connected to the third input of the AND gate 96 and to an input ~ the OF~ gate 92.
The input ~ELECTION MODE is connected to the second input of the OR gate 94, whereas the input SELECT STB is connected tO the second input of the OR gate 91, and the input EN LEFT IN is connected to the second input of the OR gate 92. The output of the OR gate 92 is connec~ed to a second input and the output of the OR
gate 93 to the third input of the AND gate 95. The D-flip-flop 97 which serves as a marker flip-flop can be set by ~hree different - ~4 -signals:
If the bus switch is selected (selected "1"), with a pulse marking flip-flop is set at a logic "0", i.e. the ou:put Q is connected to "0";
With a ~F~FT~ pulse, the flip-flop is loaded wi~h the state of the input EN LEFT IN; and With a SHIFT RIGHT pulse, is loaded with the state of the input SHIFT RIGHT IN which is connected to the second input of the OR gate 93.
The advantageous circuit comprising SHIFT LEFT and SHIFT RIGHT
which has been described is intended to facilitate a simple shift of bus sections which have already been divided by connecting a SHIFT LEFT
or SHI~T RIGHT pulse~ as a result of which the computer system can be particularly advantageously ennplosred for problem structures such as described in FIGS. 3 and 4.
When the SELECTION MODE input is connected to a logic "0" the relevant binary value present at the output Q of the flip-flop is conn~l~ted to the enabled output. The bus switch now interrupts when the enabled output carries "0". Otherwise it is open. If the SELECTION ~ODE input is connected to a logic "1" enable likewise carries this value~ which rneans that the bus switch is closed. In ~is manner it is possible to switch over be~ween a system bus divided into sections and a through-going system bus without any loss of time.
The marking flip-flop can be reset to ~he basic positlon Q = "1" by way of the ~ input. The function of the marking flip-flop is to "mark" the bus switches which are to interrupt in the case of the "selection mode'~ operating mode. As described above9 this marking can be carried out in three different ways. The bus switch remains closed, however, if a "1" is present at the SELECTION MODE input.
As a result, items of information can be t:ransmitted from the control computer to all of the computers, data exchange computers and bus switches provided in the system. As a result9 the sequence of marking of the bus switches is arbitrary. ~, on the other hand, the bus switch were to interrupt immediately, all the components located behind the switch would be unable to be approached by the control computer. It would therefore be necessary to first interrupt the more remote bus switches. If the input SELE`C~FON MODE- is connected to a "O", the system bus is interruptecl at the marked points.
During a data exchange with a divided system bus, a temporary and shor~-term necessity can consist in gainmg access from the control computer to all or a few ~ the more remote components, for example in order to modify the programs in the data e~change computers. For this pu~pose, the time saving transfer ~etween divided and through-connected system bus configuration i~ provided which can be achieved in a very simple manner with the aid of the flip-flQp .
FIG. 10 illus~rates a bridging of four bus switches S10l--Sl04 by a further bus switch S201. Each of the switches is constructed as illustrated in FIG. 5. The ENABLED outputs of the four bus switches are connected via a wired AND circuit to the ENABLE input of the further bus switch and to the DISL input of the bus switch S101. The outputs DISR1 OUT and DISR2 OUT of the further bus switch are connected to the corresponding inputs DISR1 and DISR2 of the bus switch S104. In the case of all the other bus switches and the further bus switch, these inputs are connected to ground. ~part from the bus switch S101, in the case of the further bus switch and all the other bus switches, the inputs ~ISL are likewise connec~ed to ground.
The inputs DIR CTRLl and DIR CTRL2 are connected to the con~rol computer via control lines DIR CTRLl+ 2. All the other inputs and outputs of the bus switches are likewise connected to the control computer ~ia a control bus SWITCH CONl~OL BtJS. The mode of operation of this connection is such that when all the bus swi~ches are released, and the further bus switch is likewise released, simultaneously, via the inputs DISL, the left-hand bus switch S101 is blocked in respect of the left-hand data flow direction and via the inputs DISR1 and DISRZ the right-hand bus switch S101 is blocked in respect of right-hand directions. (An exception is formed ~y the bridging of arms with data sources which will be described later in this description.) In this manner, the data paths 101 and 112 illustrated in FIG. 11 are formed.
The illustrated bridging can be used for any bridging stage.
This means that the switches S101--S104 can equally constitute further bus switches of the first or a higher stage o~ a bridging system. In this manner it is possible to construct any multi-stage bridging system.
~ z~
In FIG. 12, a zone 120 framed in broken lines in FIG. 10 has been illustrated in full detail.
Here the inputs and ou~uts whose use is dependent upon the setting of the switch are marked with an asterisk. When the switch is used as a bus switch in a system without bridgings, all three inpu~s DISR1, DISRZ and DISL are connected to ground. With bridgings, the interconnectian of the four upper outputs can be gathered from FIG.
10. The sarne applies when the switch S102 is a left-hand end switch and the switch S103 is a right-hand end switch. The wiring o~ the other inputs ancl outputs o~ the two switches, therefore the switches which are not marked with an asterisk, is obvious from FIG. 12.
FIG. 13 illustrates four bus switches S121--S124 on a data bus 125 OI a cornputer system. The directional transfer is to be explained on the basis of this drawing. Between two adjacent bus switches, an individual computer or data exchange computer i~
connected as the source Q1--Q3 f information to the data bus. The construction of the bus switches is as illustrated in FIGo 5~ with the difference th~t the selection logic BC1 and BC2 is replaced by a simplified, extra logic in each case pr~vided with a driver and a resistor. The function of this simplified logic is identical to that illu~trated in FIG. 7, when the inputs DISR1 and DISR2, DISL, DIR
CTRL IN 1 and DIR CTRL IN 2 are connected to a logic "0" and enable 1 and enable 2 are connected to "1". In FIG. 13 the input dien o~ the bus driver BD1 of each bus switch is connected to a , control line ~:)IR CTRL. Between two adjacent connection points, a driver having an open collector output is arranged in the control line, and furthermore each of these sections can be connected by way of a resistor to the supply voltage. The drivers are provided with the references 131--134 and the resistors with the references 135--138.
Each source has an output q1~ q2 or q3 which is connected to the control line DIR CTRL. This output is connected to a logic "O" when the source is ~ransmitting, i.e. when the individual computer or exchange computer is emitting data. An arrangement which is of identical construction and which is provided with a control line to which sources are connected can be additionally provided for the inputs dien of the two-path bus driver BD2.
The arrangement illustrated in FIG. 13 realizes the principle of directional transfer. This is based upon the ~ollowing considerations:
In each bus section, there is only one transmitting source for each bus system in each exchange c~rcle.
In the case of the control and address bus this can be the control computer or an exchange computer and in the case of the data bus can consist of a specific individual computer. This source transmits information to the remaining elements OI the bus section;
this means that the bus drivers must be connected in the direction leading away from the source.
The principle of directional transfer is identical for both bus systems; therefore, only the data bus system has been illustrated in FIG. 13. In FIG. 13 the bus driver direction is controlled via the control line DIR CTRL. If no source is transmitting, it is colmected to a logic "1", which is effected by the resistors. As a result, the drivers are connected to the right-hand direction. If a source now wishes to transmit information, it connects a logic "0" to the associated sec~ion of the control line. This value is communicated to the drivers arranged on the left-hand of the source and consequently these drivers reverse their direction to the left. As a result, the source can emit its information in a radiating fashion.
In the case of bridged arms of a bridging system, the source must connect such control lines DIR CTRL of the further bus switches in the same way to a logic "0". In FIG. 14, the data flow in the case oî sources wi~hin bridged sections of a bxidging system corresponding to FIG. 2 has been represented by way of example.
The items of information emitted fro~ the source are forwarded tO a bridged section of the next higher stage via the extreme right bus switch of the bridged section to which the source is connec~ed. The same then applies to the forwarding from stage to stageO Therefore, in this case for each stage the extreme rlght bus driver of a section which receives information from the next lower stage is not blocked for the right-hand data flow direction, even when all the bus switches in this section are released. The output DISR OIJT of the bridging bus switch is inactive because its data flow direction is toward the left .
112:1LO15 Finally, the function of the data excbange computer will be described. When the system bus has been divided into sections, these sections represent independent computer systems and require a "central" cornputer which under~akes the distribution of the results within the independent section. In this case i~ must fulfill the two following functions:
(1) Switching of a data path upon which data is to be transmitted; and
(2) Transrnission of data on this path.
This can be fundamentally effected by any suitably programmed computer. However, data exchange computers especially set up for this purpose have been proposed, as disclosed, for example, in the Gerznan patent application P 26 41 741.4, which computers are also highly suitable for the computer system described herein.
Although I have described my invention by reference to par~icular illustrative embodiments thereof, many changes and modifications of the in~7ention may become apparent to those skilled in the art without departing from the spirit and scope of the in~en~ion.
I therefore intend to include within the patent warranted hereon all such changes and modifications as may reasonably and properly be included within the scope of my contributiQn to the art.
This can be fundamentally effected by any suitably programmed computer. However, data exchange computers especially set up for this purpose have been proposed, as disclosed, for example, in the Gerznan patent application P 26 41 741.4, which computers are also highly suitable for the computer system described herein.
Although I have described my invention by reference to par~icular illustrative embodiments thereof, many changes and modifications of the in~7ention may become apparent to those skilled in the art without departing from the spirit and scope of the in~en~ion.
I therefore intend to include within the patent warranted hereon all such changes and modifications as may reasonably and properly be included within the scope of my contributiQn to the art.
Claims (4)
1. In a computer system of the type in which a plurality of individual computers are operatively connected to a control computer by way of at least two bus systems including an address and control bus and at least one data bus, the improvement therein comprising at least one bus switch connected in and operable to interrupt said bus systems into sections, including means for controlling the flow-through direction separately for each of the bus systems, at least one data exchange computer and means for connecting the data exchange computer into the bus system at a point along the bus systems.
2. The improved computer system of claim 1, wherein each of the individual computers is connected to respective points along the bus systems, and comprising a respective bus switch connected between adjacent ones of said points.
3. The improved computer system of claim 2, comprising a separate data exchange computer operatively connected at each of said points.
4. The improved computer system of claim 3, comprising a bus switch group including at least one further bus switch bridging at least two adjacent bus switches comprising means for controlling the flow-through direction, means for enabling the further bus switch when all the bus switches within the group are enabled and simultaneously interrupting the bus switch within the group at one end of the selected section, and means for interrupting said further bus switch when at least one bus switch within the group is interrupted.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19772742035 DE2742035A1 (en) | 1977-09-19 | 1977-09-19 | COMPUTER SYSTEM |
| DEP2742035.5 | 1977-09-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1121015A true CA1121015A (en) | 1982-03-30 |
Family
ID=6019283
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000311503A Expired CA1121015A (en) | 1977-09-19 | 1978-09-18 | Computer system |
Country Status (8)
| Country | Link |
|---|---|
| JP (1) | JPS5456743A (en) |
| BE (1) | BE870595A (en) |
| CA (1) | CA1121015A (en) |
| DE (1) | DE2742035A1 (en) |
| FR (1) | FR2403600A1 (en) |
| GB (1) | GB1597333A (en) |
| IT (1) | IT1098541B (en) |
| NL (1) | NL7809481A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7185179B1 (en) | 1999-09-17 | 2007-02-27 | Turbo Data Laboratories, Inc. | Architecture of a parallel computer and an information processing unit using the same |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5680722A (en) * | 1979-12-06 | 1981-07-02 | Nippon Telegr & Teleph Corp <Ntt> | Interprocessor control system |
| EP0057756B1 (en) * | 1981-02-11 | 1985-02-20 | Siemens Aktiengesellschaft | Data exchange unit in multi-microcomputer systems operating in parallel |
| DE3104903C2 (en) * | 1981-02-11 | 1986-05-15 | Siemens AG, 1000 Berlin und 8000 München | Arrangement for data exchange between microcomputers working in parallel |
| JPS5864562A (en) * | 1981-10-14 | 1983-04-16 | Hitachi Ltd | Signal processor |
| JPS5924363A (en) * | 1982-07-31 | 1984-02-08 | Nec Home Electronics Ltd | Common connecting system of bus for plural microcomputers |
| JPS5945527A (en) * | 1982-09-07 | 1984-03-14 | Hitachi Ltd | Controlling system of bus |
| FR2605768B1 (en) * | 1986-10-23 | 1989-05-05 | Bull Sa | BUS CONTROL DEVICE CONSISTING OF SEVERAL INSULATING SEGMENTS |
| JPS63138448A (en) * | 1986-12-01 | 1988-06-10 | Fanuc Ltd | Bus control system for multiplex processor processing system |
| JP2967928B2 (en) * | 1987-06-19 | 1999-10-25 | 日本電信電話株式会社 | Parallel processor |
| FI84114C (en) * | 1988-02-17 | 1991-10-10 | Valtion Teknillinen | Switching System |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3832695A (en) * | 1972-11-06 | 1974-08-27 | Sperry Rand Corp | Partitioning circuit employing external interrupt signal |
| JPS5093362A (en) * | 1973-12-19 | 1975-07-25 | ||
| DE2546202A1 (en) * | 1975-10-15 | 1977-04-28 | Siemens Ag | COMPUTER SYSTEM OF SEVERAL INTERCONNECTED AND INTERACTING INDIVIDUAL COMPUTERS AND PROCEDURES FOR OPERATING THE COMPUTER SYSTEM |
| JPS52109340A (en) * | 1976-03-09 | 1977-09-13 | Zilog Inc | Device and method of microprocessing |
| JPS5324743A (en) * | 1976-08-20 | 1978-03-07 | Hitachi Ltd | Bus selector for electronic computer |
| DE2641741C2 (en) * | 1976-09-16 | 1986-01-16 | Siemens AG, 1000 Berlin und 8000 München | Computing system made up of several individual computers connected and interacting with one another via a manifold system and a control computer |
| DE2651004A1 (en) * | 1976-11-08 | 1978-05-11 | Siemens Ag | DATA PROCESSING SYSTEM WITH A SYMMETRICAL MULTIPROCESSOR STRUCTURE |
-
1977
- 1977-09-19 DE DE19772742035 patent/DE2742035A1/en not_active Withdrawn
-
1978
- 1978-05-26 GB GB23285/78A patent/GB1597333A/en not_active Expired
- 1978-09-13 IT IT27598/78A patent/IT1098541B/en active
- 1978-09-13 FR FR7826276A patent/FR2403600A1/en active Granted
- 1978-09-18 CA CA000311503A patent/CA1121015A/en not_active Expired
- 1978-09-18 NL NL7809481A patent/NL7809481A/en not_active Application Discontinuation
- 1978-09-19 JP JP11503278A patent/JPS5456743A/en active Granted
- 1978-09-19 BE BE190579A patent/BE870595A/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7185179B1 (en) | 1999-09-17 | 2007-02-27 | Turbo Data Laboratories, Inc. | Architecture of a parallel computer and an information processing unit using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2403600A1 (en) | 1979-04-13 |
| IT7827598A0 (en) | 1978-09-13 |
| DE2742035A1 (en) | 1979-03-29 |
| BE870595A (en) | 1979-01-15 |
| JPS5456743A (en) | 1979-05-08 |
| JPH0125096B2 (en) | 1989-05-16 |
| NL7809481A (en) | 1979-03-21 |
| FR2403600B1 (en) | 1985-02-15 |
| GB1597333A (en) | 1981-09-03 |
| IT1098541B (en) | 1985-09-07 |
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