JP2002229963A - Parallel computer system and crossbar switch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a parallel computer system in which crossbars of the same structure are applied and a communication path width and the number of connectable nodes are made variable. SOLUTION: To a crossbar switch 3 for the connection between computation nodes of the parallel computer, more than one pairs of a control signal path Ci and a data path Di are made connectable, in a connection pattern that, to each computer node, a pair of the control signal path and the data path is allocated, the crossbar switch 3, in response to the control information on each control signal path Ci, routes the transmission data individually on the corresponding data path Di, and in a connection pattern that, to each computing node, more than one data paths Di are allocated, on the basis of the control information on a control signal path Ci, the crossbar switch 3 collectively routes every pieces of the transmission data on more than one data paths Di.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a parallel computer system, and more particularly to a crossbar switch for connecting a plurality of operation nodes and a parallel computer system to which the crossbar switch is applied.

[0002]

2. Description of the Related Art A parallel computer system having a cluster configuration in which a plurality of computers are connected via a network or an SMP (Symmetric Parallel) configuration in which one computer is configured with a plurality of CPUs in order to execute a huge amount of calculation processing at high speed. It has been known. For example, Japanese Patent Laying-Open No. 2-228760 proposes a cluster-structured parallel computer in which a plurality of computers are connected by a dedicated crossbar switch to achieve high performance. Even in the parallel computer system of the SMP configuration, when the number of connected CPUs increases, a plurality of C
A system configuration in which a plurality of operation nodes including PUs are connected via a network is employed. For example, Japanese Patent Application Laid-Open No. 9-293060 proposes a parallel computer system having an SMP configuration in which 32 to 64 or more CPUs are connected by using a dedicated crossbar.

In a system in which a dedicated crossbar switch is used for connection between operation nodes, for example, when an inter-node communication frequently occurs or an application that requires a large throughput for the inter-node communication is executed, each node is connected to the other node. The throughput with the crossbar greatly affects the performance of the entire system. For this reason, in a parallel computer system using a crossbar, the crossbar L is adjusted so that a throughput corresponding to the target performance of the target application is obtained.
It is necessary to design SI.

However, the throughput of the crossbar is LS
Although improvement can be achieved by increasing the operating frequency and data width of I, there are limitations on the operating frequency of each LSI and the number of external connection pins that can be mounted due to restrictions on LSI manufacturing technology. For this reason, in an actual application, for example, by dividing one crossbar into a plurality of LSIs and dividing transmission / reception data of each operation node into the plurality of LSIs, the transmission / reception data width of each crossbar LSI is reduced. A configuration that can be reduced is adopted. For example, when performing 8-byte parallel high-speed data transfer between operation nodes, if an attempt is made to configure a crossbar interposed between the nodes with one LSI, each input / output port requires at least a 64-bit data pin. Become. In this case, if the crossbar is divided into four LSIs, the transmission / reception data width per port can be 2 bytes (16 bits) in each LSI, so that the existing LSI technology can be used. If the crossbars are connected in multiple stages, it is possible to increase the number of connected nodes without reducing the transmission / reception data width between each node and the crossbar.

[0005]

Some of the applications of the parallel computer system do not require a large crossbar throughput. Even if the crossbar throughput is low, it is better to connect as many processing nodes as possible. Some are obtained. In such a parallel computer system for applications where the communication speed between nodes may be low, an expensive high-speed crossbar is not required, and a low-cost crossbar according to the throughput performance is sufficient.

An object of the present invention is to provide a parallel computer system capable of realizing communication between operation nodes having different data widths by applying LSIs having the same structure. It is another object of the present invention to provide a crossbar switch that can be adapted to data transfer with various throughputs. Another object of the present invention is to provide a parallel computer system and an inter-node connection method in which the number of connection nodes is made variable according to the throughput required by the operation nodes.

[0007]

In order to achieve the above object, according to the present invention, in a parallel computer system in which a plurality of operation nodes are connected by a crossbar switch, a connection path width between each operation node and the crossbar switch is reduced. It is characterized by being variable according to the throughput required by the operation node. More specifically, the present invention provides a parallel computer system in which a plurality of operation nodes are connected by a crossbar switch, such that the crossbar switch can accommodate a plurality of pairs of control signal paths and data paths for input and output, respectively. In a node connection configuration in which a plurality of input and output ports are arranged, and a pair of the control signal path and the data path are assigned to each operation node, the crossbar switch transmits control information on each control signal path. On the basis of,
In a node connection configuration in which transmission data on each data path paired with the control signal path is individually routed and one set of the control signal path and one data path is assigned to each operation node, the crossbar switch is , Transmission data on a plurality of data paths in each set is routed collectively based on control information on one control signal path representing the above.

In the crossbar switch of the present invention, a plurality of sets of control signal paths and data paths are provided for input and output, respectively, as a set of m pairs of control signal paths and data paths (where m> 1 is an integer). According to control information received from each of a plurality of input and output ports arranged so as to be capable of accommodating each control signal path for input, transmission data on one data path forming a pair with the control signal path is individually transmitted. A first transfer mode for performing transfer control, and a second transfer for collectively controlling transmission of transmission data on a plurality of data paths in one set in accordance with control information received from one control signal path representing each set. A node connection mode in which a pair of the control signal path and the data path is assigned to the transmission unit and the reception unit of each operation node, and the transmission unit and the reception unit of each operation node have Control signal path And characterized in that enabling and node topology assigned a data path one set. still,
When the crossbar switch operates in the second transfer mode, the crossbar switch and the operation node are connected in a form omitting the control signal paths other than the control signal path representative of each group.

In a preferred embodiment of the present invention, each operation node connected to the crossbar switch includes, for example, a high-speed transfer mode for transmitting and receiving data in parallel through a plurality of data paths connected to the crossbar switch; A transmission / reception unit is provided which can switch between a low-speed transfer mode in which data divided into a plurality of blocks is transmitted / received in a time series with one data path connected to the crossbar switch.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a basic system configuration of a parallel computer system according to the present invention comprising two operation nodes (node 1 and node 2) and a crossbar switch (hereinafter simply referred to as a crossbar) 3. In the system configuration shown here, node 1, node 2 and crossbar 3
The connection is such that the transmission / reception data width of each node can be fully used.

In the figure, TX1 and RX1 are nodes 1
TX2 and RX2 denote the transmission unit and the reception unit of the node 2, respectively. The crossbar 3 includes input ports for control signal paths C1 to C4 and data paths D1 to D4.
Input ports, output ports for control signal paths C11 to C14, and output ports for data paths D11 to D14, and data paths D1 to D4, D11 to D14.
14 have the same data width.

The transmission section TX1 of the node 1 is connected to the crossbar 3 via the control signal path C1 and the data paths D1 and D2, and is connected to the upper 1 / N byte (or bit) transmission data.
2 to the data path D1 and the lower half to the data path D2 in parallel. The transmission unit TX2 of the node 2 transmits the signal to the crossbar 3 via the control signal path C3 and the data paths D3 and D4.
And transmits the upper half of the transmission data to the data path D3 and the lower half to the data path D4, similarly to the transmission unit TX1 of the node 1. In this case, the control signal path C2,
C4 becomes unused, transmission data to the data paths D1 and D2 is routed by control information on the control signal path C1, and transmission data to the data paths D3 and D4 is
It is routed by control information on the control signal path C3.

The receiving section TR1 of the node 1 is connected to the crossbar 3 via a control signal path C11 and data paths D11 and D12.
, The upper half of the transmission data from the other node from the data path D11 and the lower half of the transmission data from the data path D12.
, And the control information corresponding to these data is received from the control signal path C11. Similarly,
The receiving unit TR2 of the node 2 is connected to the crossbar 3 via a control signal path C13 and data paths D13 and D14,
Data path D
13. The lower half is received in parallel from the data path D14, and control information is received from the control signal path C13.

FIG. 2 shows another system configuration of a parallel computer system according to the present invention in which four operation nodes (nodes 1 to 4) are interconnected by a crossbar 3 having the same structure as in FIG. In the system configuration shown in FIG. 2, the transmission units TX1 to TX4 of each of the above-described nodes respectively provide a pair of control signal paths and data paths (C1 and D1, C2 and D1).
2, C3 and D3, C4 and D4), and the receiving units RX1 to RX4 of the above-mentioned nodes respectively provide a pair of control signal paths and data paths (C11 and D1).
1, C12 and D12, C13 and D13, C14 and D1
4) is connected to the crossbar 3.

In the above system configuration, the crossbar 3
Routes the received data from the data paths D1 to D4 according to the control information on the control signal paths C1 to C4 paired with the respective data paths. In this case, since the data width of each node transmitted to the crossbar 3 is half the data width of each node in FIG. 1, the data transfer speed between the nodes is low. Therefore, the system configuration shown in FIG. 2 has a configuration suitable for connecting a large number of operation nodes that do not require high-speed data transfer by using the crossbar 3 that can be adapted to high throughput as shown in FIG. I can say.

FIGS. 3 and 4 show an embodiment of an operation node in which the data transfer speed suitable for connection to the crossbar 3 is variable. FIG. 3 is a block diagram of the transmission unit TX of the node 1 in FIG.
1 is shown. In the figure, reference numeral 10 denotes a node internal unit, such as a CPU, a memory, and an I / O device, which constitutes a main part of an arithmetic node. Transmission data (for example, an address transaction or a data transaction) destined for another node generated in the node internal unit is output to the internal path 102 in units of N bytes (or bits), and control information accompanying the output is output to the path 101. Is done.

The transmission buffer controller 12 has a path 1
01, the control information and the transmission data are written into the transmission buffer 11 and these are stored in the FIFO.
Read in format. The control information read from the transmission buffer 11 is output to the path 103, and the transmission data is output with the upper half divided into the path 104 and the lower half divided into the path 105. The control information read to the path 103 is input to the output latch 14, and the upper half transmission data read to the path 104 is input to the output latch 14 via the selector 13. The lower half transmission data read to the path 105 is input to the selector 13 and the output latch 14 in parallel.

The selector 13 is controlled by the transmission buffer controller 12, and the node 1 is operated in a high-speed transfer (full throughput) mode in which the output data paths D1 and D2 are fully used as shown in FIG. In this case, the selector 13 is controlled to always select the path 104. When the node 1 is operated in the low-speed transfer (low throughput) mode using only the data path D1 as shown in FIG. 2, the selector 13 switches the input path every transmission cycle, and It is controlled so that the input data from 105 is output to the path 106 alternately.

When the node 1 is set in the high-speed transfer mode, the transmission buffer controller 12 updates the read pointer of the transmission buffer 11 so that one transaction is processed in each transmission cycle. Therefore,
In the high-speed transfer mode, new transmission data having an N-byte width and new control information associated therewith are read from the transmission buffer 11 every transmission cycle, and these are transmitted via the output latch 14 to the control signal path C1. And data paths D1, D
2 is output.

When the node 1 is set to the low-speed transfer mode, the transmission buffer controller 12 writes control information and transmission data in the transmission buffer 11 at a low transmission rate once every two cycles, and selects the selector every transmission cycle. While switching 13, the read pointer of the transmission buffer 11 is updated so that the same control information and transmission data are read for two consecutive cycles. Thereby, in the first transmission cycle, the control information read to the path 103 and
The upper half transmission data portion read out on the path 104 is output to the control signal path C1 and the data path D1 via the output latch 14, and in the next transmission cycle, the path 10
3 and the lower half transmission data portion read out to the path 105 are output from the output latch 1.
4 to the control signal path C1 and the data path D1. When the node 1 is operated in the low-speed transfer mode, the data path D2 shown in FIG. 3 is not connected to the crossbar 3, so that the lower half input to the output latch 14 via the path 105 Data is useless.

FIG. 4 shows the configuration of the receiving section TR1 of the node 1. The reception unit TR1 of the node 1 includes a reception buffer 21 for temporarily storing control information and data output from the crossbar 3, a reception buffer controller 22 for controlling writing and reading of data to and from the reception buffer 21, and And a selector 23 controlled by the reception buffer controller 22.

When the node 1 is set to the high-speed transfer mode, the selector 23 is controlled to always output the input data of the data path D12 to the path 120. Therefore,
The control information output from the crossbar 3 to the control signal path C11, the upper half of the N-byte (bit) transmission data output to the data path D11, and the lower half of the transmission data output to the data path D12. Are input to the reception buffer 21 in parallel. The reception buffer controller 22 writes the control information and the transmission data into the reception buffer for each transmission cycle, reads out the data in a FIFO format, and transfers it to the node internal unit 10.

When the node 1 is operated in the low-speed transfer mode, the data path D12 is not used, and the data block corresponding to the upper half of the N-byte transmission data and the lower one
/ 2 data blocks alternately appear in the data path D11. Therefore, in the node 1 in the low-speed transfer mode, the reception buffer controller 22 alternately switches the input path of the selector 23 for each transmission cycle.
In the first cycle, the control information input from the control signal path C11 and the upper half of the transmission data input from the data path D11 are written into one entry area of the reception buffer 21. The read address pointer and buffer input are controlled so that the lower half of the transmission data input from the path 120 is added to the area, and the control information and transmission data for one entry are read once every two cycles. I do. Node 1
Although the transmission unit TX1 and the reception unit RX1 have been described, other nodes may have the same configuration.

FIG. 5 shows an example of a detailed configuration of the crossbar 3. The crossbar 3 of the present invention includes a plurality of crossbar reception control units 30R corresponding to the number of nodes that can be accommodated in the high-speed transfer (full throughput) mode, a plurality of crossbar transmission control units 40T, and an internal path 301 connecting these. ~ 304
Consists of Here, a crossbar 3 including two crossbar reception control units 30R1 and 20R2 and two crossbar transmission control units 40T1 and 40T2 will be described with reference to FIG.

The crossbar reception controller 30R1 includes a first reception buffer 31 connected to input ports Pc1 and Pd1 for accommodating the control signal path C1 and the data path D1.
A first reception buffer controller 32 that controls writing and reading of data to and from the reception buffer 31;
A second reception buffer 33 connected to the input ports Pc2 and Pd2 for accommodating the control signal path C2 and the data path D2, and a second reception buffer controlling writing and reading of data to and from the reception buffer 33 It includes a controller 32 and a selector 35 for causing the first and second reception buffer controllers to selectively act on the second reception buffer 33.

The first reception buffer controller 32
In response to the control information input from the control signal path C1,
A control signal S32 for writing input control information from the control signal path C1 and transmission data input from the data path D1 to the reception buffer 31 is generated. Similarly, the second receiving buffer controller 34 also responds to the control information input from the control signal path C2, and receives the input control information from the control signal path C2 and the transmission data input from the data path D2. Is generated in the reception buffer 33.

When each node connected to the crossbar 3 is operated in the high-speed transfer mode, as shown in FIG. 1, the control signal path C2 is not used, and the control signal path C1 is not used.
Are shared by the data paths D1 and D2. In this case, the control signal S34 output from the second reception buffer controller 34 connected to the control signal path C2 becomes invalid,
The selector 35 is connected to the first reception buffer controller 32
Control signal S32 output from the second receiving buffer 3
3 is set. That is, in the crossbar accommodating the nodes in the high-speed transfer mode, the first reception buffer controller 32 controls the first and second reception buffers 3.
The writing and reading to 1, 32 are simultaneously controlled.

When each node connected to the crossbar 3 is operated in the low-speed transfer mode, as shown in FIG. 2, control information accompanying transmission data of the data path D2 is output to the control signal path C2. I have. In this case, the selector 3
5 is set so as to supply the control signal S 34 output from the second reception buffer controller 34 to the second reception buffer 33. That is, in the crossbar accommodating the nodes in the low-speed transfer mode, the first and second reception buffer controllers function independently of each other,
Writing and reading of data to and from the first and second receiving buffers 31 and 32 are separately controlled. The control information and data stored in the first reception buffer 31 are read out to the first internal path 301, and the control information and data stored in the second reception buffer 33 are read out to the second internal path 302. It is.

Similarly to the crossbar reception control unit 30R1, the crossbar reception control unit 30R2 also has input ports Pc3, Pd for accommodating the control signal path C3 and the data path D3.
3 and a control signal path C
4 and an input port Pc for accommodating the data path D4
4, a second reception buffer connected to Pd4,
The control information and data stored in the first reception buffer are read out to the third internal path 303, and the control information and data stored in the second reception buffer are read out to the fourth internal path 303.
04 is read.

The crossbar transmission control unit 40T1 is provided with the first
1st and 2nd connected to 4th internal path 301-304
Selectors 41 and 43, a first arbiter 42 for controlling the first selector 41, and a second arbiter 4
3 and a selector 45 for selectively causing the first and second arbiters to act on the second selector 43. The output of the first selector 41 is connected to the control signal path C11 and the data path D1.
1, and the output of the second selector 43 is connected to output ports Pc12, Pd12 for accommodating the control signal path C12 and the data path D12.

When each node connected to the crossbar 3 is operating in the high-speed transfer mode, the control signal S44 from the second arbiter 44 becomes invalid. In this case, the selector 45 outputs the control signal S4 output from the first arbiter 42.
2 to the second selector 43, and the data transfer to the data paths D11 and D12 is performed by the first arbiter 42.
Are controlled simultaneously. When each node connected to the crossbar 3 is operated in the low-speed transfer mode, the selector 4
5 is a control signal S44 output from the second arbiter 44.
Is provided to the second selector 43, and data transfer to the data paths D11 and D12 is separately controlled by the first and second arbiters.

Each control information branched from the first to fourth internal paths 301 to 304 is input to each arbiter. The first arbiter 42 determines whether the first selector 41 determines the first to fourth internal paths 301 to 301 based on the control information.
The selector control signal S42 is generated so as to select the internal path 30j having the data to be transferred to the data path D11 from among the 304. When each node is operated in the high-speed transfer mode, the second selector 43 selects the internal path 30j + 1 paired with the internal path 30j by the control signal S42. When each node is operated in the low-speed transfer mode, the second arbiter 44 operates similarly to the first arbiter 42, and the second selector 43
A selector control signal S44 is generated so as to select a path having data to be transferred to the data path D12 from the internal paths 301 to 304.

The first arbiter 42 generates a control signal for permitting the next data transmission to the reception buffer controller which is the transmission source of the data to the selected internal path 30j with the generation of the selector control signal S42. Generate AB1. Similarly, the second arbiter 44 generates a control signal AB2 at the transmission source every time an internal path is selected. The crossbar transmission control unit 40T2, similarly to the crossbar transmission control unit 40T1, has first and second arbiters, controls data transfer to the data paths D13 and D14, respectively, and controls the control signal AB3 to the transmission source. Generate AB4. Each of the reception buffer controllers of the crossbar reception control units 30R1 and 30R2 reads the next data from the reception buffer to the internal path, after being permitted by the control signals AB1 to AB4.

In the above embodiment, for the sake of simplicity, a small crossbar switch capable of accommodating two nodes in the high-speed transfer mode has been described. However, the reception control unit 30R and the transmission control unit constituting the crossbar switch are described. By increasing the number of 30Ts, a parallel computer system having a large number of accommodation nodes can be constructed. Further, in the above embodiment, in the high-speed transfer mode, the transmission data from each node is received in parallel by two data paths, and in the low-speed transfer mode, each data path is used individually, thereby reducing the number of accommodated nodes. The crossbar switch that can be doubled in the high-speed transfer mode has been described. However, if the number of data paths used in parallel in the high-speed transfer mode is increased, a variety of parallel computer systems using the same structure of the crossbar switch can be constructed. Becomes possible.

For example, four sets of reception buffers and reception buffer controllers are prepared in each crossbar reception control unit 30R shown in FIG. 5, and in the high-speed transfer mode, the first controller 32 controls four simultaneous reception buffers. In the low-speed transfer mode, four reception buffers are individually controlled. In the intermediate-speed transfer mode, the first controller controls the first and second reception buffers, and the second controller controls the third and fourth buffers. , It is possible to construct a more flexible parallel computer system that can select three stages of data transfer speed and three stages of system scale by applying the same crossbar switch. Become. In FIGS. 3 and 4, the configuration of the operation node having a predetermined data width inside the node and selectively applicable to two high-speed and low-speed data transfer modes has been exemplified. The transmission / reception unit of the node which is not required and is fixedly operated only in the high-speed transfer mode shown in FIG.
It is good also as composition which does not have 3 and 23.

[0036]

As is apparent from the above description, according to the present invention, the crossbar having the same structure can be applied to various parallel computer systems having different data transfer speeds between nodes. And the system price can be reduced. Also,
If the transmission / reception unit of each node connected to the crossbar is configured in advance to be selectively adaptable to a plurality of types of transmission / reception data widths, the transfer data between the crossbar and the target application of the parallel computer system can be adjusted. By changing the width, the number of nodes accommodated in the crossbar can be easily increased or decreased according to the data transfer speed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of a parallel computer system according to the present invention.

FIG. 2 is a diagram showing another configuration example of the parallel computer system according to the present invention.

FIG. 3 is a diagram showing one embodiment of an arithmetic node transmitting unit in the parallel computer system of the present invention.

FIG. 4 is a diagram showing one embodiment of an arithmetic node receiving unit in the parallel computer system of the present invention.

FIG. 5 is a diagram showing one embodiment of a crossbar in the parallel computer system of the present invention.

[Explanation of symbols]

TX1 to TX4: node transmission unit, RX1 to RX4: node reception unit, 3: crossbar, 10: node internal unit,
11: transmission buffer, 12: transmission buffer controller, 13: selector, 14: output latch, 21: reception buffer, 22: reception buffer controller, 23: selector, 30R: crossbar reception control unit, 40T: crossbar transmission control unit, 31 , 33: receive buffer, 32, 34:
Receive buffer controller, 41, 43: selector, 4
2, 44: arbiter, Pc1 to Pc14: control path connection port, Pd1 to Pd14: data path connection node.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B045 BB16 BB31 KK08 5B061 FF02 GG11 GG16

Claims (6)

[Claims] 1. A parallel computer system in which a plurality of operation nodes are connected by a crossbar switch, wherein the crossbar switch is arranged so as to accommodate a plurality of pairs of control signal paths and data paths for input and output. In the node connection configuration in which the control signal path and the data path are assigned to each operation node in pairs, the crossbar switch is configured to perform the control signal path and the data path based on the control information on each control signal path. The transmission data on each data path forming a pair with the control signal path is individually routed, and a plurality of pairs of control signal paths and data paths are combined into one set. In the assigned node connection mode, the crossbar switch is configured to control each set of a plurality of sets based on control information on any of the control signal paths. Parallel computer system to collectively transmit data on Tapasu characterized by being adapted to routing. 2. A high-speed transfer mode in which each operation node transmits and receives data in parallel through a plurality of data paths connected to the crossbar switch, and a plurality of blocks is divided into a plurality of blocks by one data path connected to the crossbar switch. 2. The parallel computer system according to claim 1, further comprising a transmission / reception unit capable of selecting a low-speed transfer mode for transmitting / receiving the selected data in a time-series manner. 3. In a parallel computer system in which a plurality of operation nodes are connected by a crossbar switch, the crossbar switch sets a pair of m pairs of control signal paths and data paths (where m> 1 is an integer) as a set for input. And a plurality of input and output ports arranged to accommodate a plurality of sets of control signal paths and data paths for output and output signals, respectively, in accordance with control information received from each control signal path for input. A first transfer mode for individually controlling transfer of transmission data on one data path forming a pair with a path, and one set according to control information received from one input control signal path representing each set. Means for switching between a second transfer mode for collectively controlling transmission data on a plurality of data paths, and when the crossbar switch operates in the second transfer mode, Parallel computer system, characterized in that the said crossbar switch and operation nodes are connected by a control signal path representative of serial each set. 4. When operating in the second transfer mode, each of the operation nodes transmits and receives data in parallel through m data paths for input and output, and transmits control information accompanying the data. The parallel computer system according to claim 3, wherein transmission and reception are performed through control signal paths representing the respective sets. 5. A crossbar switch connected to a plurality of nodes for transferring control signals and data between the nodes, wherein m pairs of control signal paths and data paths (where m> 1 is an integer) are set to 1 A plurality of input and output ports arranged to accommodate a plurality of sets of control signal paths and data paths for input and output, respectively, according to control information received from each control signal path for input. A first transfer mode in which transmission data on one data path paired with the control signal path is individually controlled, and a control information received from one input control signal path representing each set. Means for switching to a second transfer mode for collectively controlling transmission of transmission data on a plurality of data paths in a set. The control signal is transmitted to a transmission unit and a reception unit of each operation node. One path and one data path And a second node connection mode in which the control signal path and the data path are assigned to the transmission unit and the reception unit of each operation node in pairs. Crossbar switch. 6. The crossbar switch according to claim 5, wherein a plurality of reception control units and transmission control units provided corresponding to the respective sets are connected to each other, and between the reception control unit and the transmission control unit. M reception buffers, each of which has a plurality of internal paths, and each of the reception control units temporarily stores control information and data received from a pair of input control signal paths and data paths, respectively. And m reception buffer controllers for controlling writing and reading of the control information and data to and from the reception buffer, respectively,
In the first transfer mode, the control output generated by each of the receive buffer controllers is individually applied to the associated receive buffer, and in the second transfer mode, the control output generated by one of the receive buffer controllers is performed. Control signal selecting means for causing an output to act on the m number of reception buffers; wherein each of the internal paths is provided for each reception buffer of the reception control unit; One of the internal paths of
M selectors for selectively connecting one to one of the output ports, m arbiters provided in association with the selectors, and the arbiters are generated in the first transfer mode. A control signal selecting means for causing a control output to be individually applied to a selector associated therewith, and in the second transfer mode, applying a control output generated by one of the arbiters to the m selectors. The crossbar switch according to claim 5, wherein each of the arbiters generates a selector control output based on control information extracted from each of the plurality of internal paths.