GB1597333A - Computer system - Google Patents

Description

(54) A COMPUTER SYSTEM (71) We, SIEMENS AKTIENGE SELLSCHAFT, a German Company, of Berlin and Munich, Federal Republic of Germany, do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following Rtatement:-- The present invention relates to a computer system wherein a number of individual computers can be coupled to a control computer via a system bus, composed of at least two bus systems, namely an address bus and a control bus, and of at least one data bus.

A computer system of the type described in the introduction is known (German OS 25 46 202). In this computer system the control computer distributes the data by consecutively supplying the operational result of each individual computer to the system bus and recording this result in the remaining individual computers irrespectively of how many individual computers utilise the result. Thus the number of transfer cycles required for the total data transfer corresponds to the number of results which must be distributed.

The degree of efficiency of computer systems of the type described in the introduction is heavily dependent upon the duration of the information exchange between the individual computers. The aim is to achieve as short as possible an exchange duration.

Many problems which must be processed involve limited vicinity coupling, i.e. data only requires to be exchanged between adjacent elementary functions. In computer systems of the type described in the introduction this means that an exchange is only required between those individual computers which are arranged at a limited distance from one another. Limited vicinity coupling between individual computers in a computer system is known from field computers (see for example G. H. Barnes, R. M. Brown, M. Kato, D. J. Kuck, D. L.

Slotnik, R. A. Stokes: "The ILLIAC IV Computer", IEEE Trans. on Comp., vol. C17, No. 8, August 68), wherein the individual computers are permanently coupled to one another, e.g. each individual computer to four neighbouring computers.

This rigid coupling is only advantageous, however, in the case of a few problems; in the case of problems in which the coupling does not conform with the computer structure such as occurs for example in the case of couplings of a higher order or irregular coupling, the rigidity complicates and slows down the data exchange to a considerable extent giving rise to long exchange durations.

According to the present invention there is provided a computer system comprising a plurality of individual computers and a control computer cqupled to a system bus consisting of at least two bus systems, namely an address and control bus and at least one data bus, in which: the system bus is divided into sections by one or more bus switches arranged therein; each bus switch possesses the characteristics that (a) the two bus systems can be interrupted under its control, (b) its transmission direction can be separately switched over for each of the bus systems, and (c) it can be directly addressed by the control computer; and one or more data exchange computers, arranged in operation to control the bus switches for the setting up of required data paths and to control the transfer of data via such paths, is/are connected to the system bus at various points.

In the case of problems involving rigid or irregular coupling, this computer system allows all the bus switches to be closed and the results to be exchanged between all the individual computers. In the case of problems involving limited local coupling, by breaking bus switches it is possible to divide the system bus into a plurality of sections within which the data exchange can take place simultaneously and independently in each case under the control of a data exchange computer.

As a result of this parallel exchange, the exchange phase can be considerably shortened in the case of many problems.

A preferred embodiment of the invention is designed in such manner that a bus switch is arranged between each two adjacent points at which an individual computer can be connected to the system bus.

Another preferred embodiment is characterised in that a data exchange computer is connected to every second said connection point.

A preferred further development of the invention is designed in such manner that one or more groups the or each of which comprises two or a plurality of adjacent bus switches on the system bus, are each bridged by a further bus switch and the or each further bus switch possesses the characteristics that d) its transmission direction can be switched over, e) the switch is enabled when all the switches within the group which it bridges are enabled and simultaneously disables a switch within the group located at one end, and f) it is disabled when at least one of the other switches within the group is disabled.

This computer system is advantageously further developed in such manner that a multi-stage bridging system is formed so that in each state, with the exception of the highest stage, one or more than one group, each of which comprises two or several further bus switches, can be bridged by a further bus switch of the next higher stage, where the lowest stage consists of the further bus switches by which the bus switches on the system bus can be bridged, and that each further bus switch which bridges a group of further bus switches possesses characteristics d) to f) in respect of this group.

Exemplary embodiments of the invention will be explained in detail in the following making reference to the accompanying drawings, in which: Figure 1 is a diagram of a computer structure; Figure 2 is a diagram of a two-stage bridging system; Figure 3 illustrates a two-dimensional grid network; Figure 4 illustrates a linear diagram; Figure 5 illustrates an exemplary embodiment of a bus switch and a further bus switch; Figure 6 illustrates the design of a twopath bus driver; Figure 7 illustrates the design of the control logic of the bus switch shown in Figure 5; Figure 8 illustrates the design of the selection logic for the bus switch shown in Figure 5; Figure 9 illustrates the design of the release logic for the bus switch illustrated in Figure 5; Figure 10 illustrates the bridging of a group of switches and further bus switches by a further bus switch; Figure 11 shows two data flow diagrams for a bridging; Figure 12 illustrates an exemplary embodiment of the interconnection of the adjacent bus switches; Figure 13 illustrates an exemplary embodiment of the principle of directional switch-over; and Figure 14 is a data flow diagram relating to the two-stage bridging system illustrated in Figure 2.

In Figure 1 individual computers MX to M, are connected to a system bus I at points mlm,. Between each two adjacent connection points m, and m*+, a bus switch S, is arranged in the systen bus. There are accordingly five bus switches S, to S, available. The bus switches serve to divide the system bus into sections a, to a,. At each of the points m2, m4 and m, of the system bus, is connected a respective data exchange computer ATR1, ATR2 and ATR1. On the left-hand side the system bus joins a control computer STR. The system can be imagined to continue on the righthand side. Preferably a computer system of this type is constructed by means of microprocessor modules.

Fig. 2 schematically illustrates a twostage bridging system. Bus switches S, to S, are arranged on a system bus 2. The bus switches Sg to S" can be bridged by a further bus switch S21, the bus switches S12 to S,4 by a further bus switch Sn, and the bus switches Sl, to S17 by the further bus switch S22.

Here the further bus switches Sl, to S,, form the first stage of the bridging system.

These in turn can be bridged by a further bus switch S24 which forms the second stage of the bridging system. Each of the further bus switches must be able to fulfil the following functions: its transmission direction must be able to be switched over; it must be enabled when all the bus switches or further bus switches in the next lower stage which it serves to bridge are themselves enabled and must simultaneously disable a switch within this group located at one end; it must be disabled when at least one of the other switches within this group is disabled.

Before the concrete construction of a computer system as illustrated in Figs. í or 2 is discussed in detail with reference to Fig. 3 and 4 it will be indicated how, in the described computer structure, the transfer width can be matched to the coupling width of the problem to be handled. Here the influence of the coupling method upon the duration of the data transfer will be investigated in the form of an example. The example considered will be a twodimensional problem structure such as illustrated in Fig. 3. Structures of this kind occur in the solution of partial differential equations in accordance with the method of finite differences which is used for example in field calculations or in weather forecasting. Here data transfer is only required between directly adjacent grid network points. In Fig. 3 this has been emphasised in the example of the network point i, which exchanges data only with its four closest neighbours i-l, i-nt and i+n.

This Problem can be represenred in the given linear computer structure for example as illustrated in Fig. I or 2, in which each individual computer deals with one grid network point, in such a manner that data exchange is only required within a specific band width. The individual computer which is assigned to the grid network point i must distribute its results between the individual computers assigned to the points i-n, i-l, i+ I and i+n. Thus the band width amounts to 2n+l. The facts projected onto one dimension are illustrated in Fig. 4.

The proposed computer system can be advantageously adapted to this problem by dividing the system bus into sections of the length 2n+l. This bus switches effect the division. The result of the particular middle individual computer is distributed within these sections. As a next stage, the sections of the system bus are displaced by one bus switch and the results of the individual computers now located in the centre of the sections are distributed and so on. As transfer takes place simultaneously in all sections, only two n+l transfer steps are required in order to distribute n2 results. As a result the data transfer phase is reduced by a factor which is equal to the ratio of the number of grid network points/band width.

In the case of a two-dimensional problem where n=100, which corresponds to a number of grid points of 104 and a band width of 201, the number of exchange steps is reduced by approx. 1/50 of the number of grid network points. Here is must be expressly pointed out that the proposed computer system is not limited to this example but can be advantangeously adapted to other problem structures. The basis consists of the aforementioned characteristics a) to c) which the bus switches must possess.

Fig. 5 illustrates a particularly expedient embodiment of a bus switch. This embodiment is designed to be such that identical units can be used for the bus switches and further bus switches. In accordance with Fig. 5, this bus switch comprises selection logic SSL, release logic SEL, two bidirectional bus drivers BDI and BD2, connected into the system bus, with associated control pogic BCI and BC2, where BDI is connected into the data bus and BD 2 into the address bus and further comprises an operating mode change-over switch S. With the aid of the operating mode change-over switch S it is possible to switch over between two operating modes, in one of which, which here is referenced A, the bus switch state is determined by the release logic SEL, and thus is addressed and controlled by the control computer. In the other operating mode which here been referenced B, the operating state is established via an ENABLE-input which can be connected to ENABLED-output of another bus switch constructed in similar manner, as a result of which the bus switch can adopt the operating state of the other.

When the bus switch is employed as further bus switch in a stage of a one-stage or multistage bridging system, the ENABLED- outputs of the bridged switches in the next lower stage are connected via a AND-gate to the ENABLE-input of this further bus switch, as a result of which the characteristics e) and f) are achieved in the latter. Between the ENABLED output and the operating mode change-over switch S there is also connected a driver 50 having an open collector output, which facilitates a wired AND-logic link between the ENABLED-outputs of a plurality of bus switches.

Fig. 6 illustrates the design of the two bidirectional bus drivers BD1 and BD2 which are of identical construction. Each is a bus driver for bit-parallel transmission of a byte and is composed of two four-bitparallel bidirectional bus drivers, integrated circuits type SAB 8216 (see detailed description in Mikro-prozessor-Bausteine "Datenbuch" 1976/77, System SAB 8080 by Siemens AG, Bereich Bauelemente, Balanstrasse 73, 8000 Munich 80). Here and in the following the inputs and outputs of the modules will be provided with the references given in the above mentioned publication. Via the inputs {$ of the two modules which are connected to a common input cs; the bus driver can be disabled. The direction of the data flow is determined via the inputs DIENich are linked to a common input dien of the bus driver.

Further details are given in the above mentioned publication. The terminals DI, DO and DB act as substitutes for the inputs Dlo to Dl3, DOo to DO3 and DBo to DB3 given therein.

Figure 7 is detailed illustration of the construction of the control logic BCI and BC2. The TTL integrated circuit type 7408 is suitable for the three AND-gates 81, 82 and 83 each having two inputs, type 7427 is suitable for the NOR-gates, type 7404 is suitable for the inverters 85 and 86, and type 7422 with an open collector is suitable for the NAND-gate 87 having three inputs, all produced by Siemens AG (see "Digitale Schaltungen", Datenbuch 1976/77 of Siemens AG, published bv ich Bauelemente, Vertrieb, 8000 Munich 80, Balanstrasse 73). The input DIR CTRL IN1 (or DIR CTRL IN2) (see Fig. 5) is connected on the one hand via the inverter 85 to an input of both the NAND-gate 87 and the AND-gate 81 and on the other hand is directly connected to an input of the AND-gate 83. In addition a direct connection exists between the aforementioned input and the output 702 which is connected to the input dien aforementioned input and the output i1; of the associated bidirectional bus driver.

The input "enable enable 2" is connected on the one hand (as shown in Figure 5) to the output 53 of the operating mode change-over switch and on the other hand to the second input of the AND-gate 83 and to a second input of the gate 87 and to an input of the NOR-gate 84. The main function of the input "enable 1" is, via the output 701 which must be connected on the one hand to the output of the NOR-gate 84 and on the other hand to the input F of the bidirectional bus driver BDl/B2 to disable or enable the latter. When the relevant bus driver is enabled via the input "enable 1"/"enable 2" of the control logic, the directional information can be forwarded to the next bus switch. This information is input into the bus switch via the inputs DIR CTRL INI and 2 (See Fig. 5). The input DISL of the control logic is connected to the second input of the AND-gate 81, whereas the input DISR I and 2 is connected to an input of the AND-gate 82.

The output of each of these AND-gates is connected to a second and third input of the NOR-gate 84. The one input of the ANDgate 82 is connected via the inverter 86 to the third input of the NAND-gate 87, and the second input of the AND-gate 82 is connected to the first input of the NANDgate. The bus driver BDI and 2 can be selectively disabled for a right-hand or left hand data flow direction via the inputs DISR 1 and 2. The output of the AND-gate 83 forms the output DISR OUTI and 2 of the bus switch. The latter output is required in a one-stage or multi-stage bridging system. The output of the NOR-gate 87 forms the output DIR CTRL OUT 1 and 2 of the bus switch.

Fig. 8 illustrates the switch selection logic SSL in detail. Here two 4-bit-comparators 81 and 82 arranged next to one another have beçn used (i.c. type 7485 in Digitale Schaltungen", page 122 and 123). The inputs 2 (A < B), 3 (A=B) and 4 (A > B) of the comparator 82, as referenced in the above mentioned publication, are connected in parallel with the corresponding output 7 (A < B), 6 (A=B) and 5 (A > B) of the comparator 81. The 4-bit-terminals A and B are identical to the terminals Ao to A3 and B0 to B, in the publication. The terminals A of the two comparators 81 and 82 together form a byte terminal which must be connected to the address bus. The 4-bitterminals B of the two comparators are connected in parallel to an 8-way coder switch having a pull-up resistor. The input 3 (A=B) of the comparator 81 is connected via a resistor 84 to the supply voltage which corresponds to a logic "1", whereas the output 6 (A=B) of the comparator 82 is connected to the "selected" input of the release logic SEL. With the schematically illustrated coder switch 83, the bus switch can be provided with a fixed switch number.

If the address input via the inputs A agrees with the switch number, the output 6 (A=B) goes to a logic "1".

Fig. 9 illustrates the release logic SEL in detail. This contains four OR-gates 91 to 94 each having two inputs, two AND-gates each having three inputs, a D-flip-flop 97 and an inverter 98. The "selected" input is connected via the inverter 98 to an indus of the OR-gate 91. The output of this OR-gate is connected on the one hand to an input of the AND-gate 95 and to an input of the AND-gate 96. The output of the AND-gate 95 is connected to the input D, and the output of the AND-gate 96 to the input T of the D-flip-flop 97 (e.g. type 7474 from "Digitale Schaltungen", page 19S191, inputs and outputs referenced as therein).

The rest input R of the flip-flop is connnected to the RESET-tnput of the bus switch. The set input S of the flip-flop is permanently connected to logic "1". The output Q of the flip-flop is connected to an innut of the OR-pate 94, to the outputs EN RIGHT OUT and EN LEFT OUT of the bus switch (see Fig. 5). The output of the ORgate 94 forms the enabled output of the release logic which is connected to the input 51 of the operating mode change-over switch whose other input 52 is connected to the input ENABLE of the bus switch. The input SHIFT RIGHT of the bus switch is connected on the one hand to a second input of the AND-gate 96 and to an input of the OR-gate 93. Similarly the input SHIFT LEFT of the bus switch is connected to the third input of the AND-gate 96 and to an input of the OR-Rate 92. The input SELECTION MODE is connected to the second input of the OR-gate 94, whereas the input SELECT STB is connected to the second input of the OR-gate 91, and t e input EN LEFT IN is connected to the second input of the OR-gate 92. The output of the OR-gate 92 is connected to a second input and the output of the OR-gate 93 to the third input of the AND-gate 95. The Dflip-flop which serves as so-called marking flip-flop can be set by three different signals: if the bus switch is selected (selected "1"), with a SELECT STB pulse the marking flip-flop is set at a logic "0", i.e. the output Q is connected to "0". With a SHIFT LEFT pulse, the flip-flop is loaded with the state of the input EN LEFT IN, and with a SHIFT.RIGHT is is loaded with' the state of the input SHIFT RIGHT IN which is connected to the second input of the OR-gate 93. The advantageous circuit comprising SHIFT LEFT and SHIFT RIGHT which has been described is intended to facilitate a simple shift of bus sections which have already been divided up by connecting a SHIFT LEFT or HT pulse, as a result of which the computer system can be particularly advantageously employed for problem structures such as described in Figures 3 and 4. ~~~~~~~~~~~~~~~~~~ When the SELECTION MODE input is connected to logic "0" the relevant binary value present at the output Q of the flip-flop is connected to the "enabled" output. The bus switch now interrupts when "enabled" carries "0". Otherwise it is closed. If the SELECTION MODE input is connected to a logic "I" "enable" likewise carries this value, which means that the bus switch is closed. In this way it is possible to switch over between a system bus divided into sections and a continuous system bus without any loss of time. The marking flipflop can be reset to the basic position Q="l" via the RESET input. The function of the marking flip-flop is as follows: it is to "mark" the bus switches which are to interrupt in the case of the "selection mode" operating mode. As described above, this marking can be carried out in three different ways. The bus switch remains closed, however, if a "1" is present at the SELECTION MODE input. As a result items of information can be transmitted from the control computer to all the computers, data exchange computers and bus switches provided in the system. As a result the sequence of marking of the bus switches is arbltrary. If, on the other hand, the bus switch were to interrupt immediately, all the components located behind this switch would be unable to be approached by the control computer. It would thus be necessary to firstly interrupt the more remote bus switches. If the input SELECTION MODE is connected to a "0" the system bus is interrupted at the marked points.

During a data transfer with a divided system bus, a temporary and short-term necessity can consist in gaining access from the control computer to all or a few of the more remote components, for example in order to modify the programmes in the data exchange computers. For this purpose the time saving switch-over between divided and through connected system bus is provided which can be achieved in a very simple manner with the aid of the flip-flop.

Frog. 10 illustrated a bridging of four bus switches Sici to Sl04 by a further bus switch S,,. Each of the switches is constructed as illustrated in Fig. 5. The ENABLED-outputs of the four bus switches are connected via a wired AND-circuit to the ENABLE-input of the further bus switch and to the DISL input of the bus switch SID1- The outputs DISR 1 OUT and DISR 2 OUT of the further bus switch are connected to the corresponding inputs DISR 1 and DISR 2 of the bus switch i. In the case of all the other bus switches and the further bus switch, these inputs are connected to earth.

Apart from the bus switch Sioi, in the case of the further bus switch and all the other bus switdhes the inputs DISL are likewise connected to earth. The inputs DIR CTRL I and DIR CTRL 2 are connected to the control computer via control lines DIR CTRL1+2. All the other inputs and outputs of the bus switches are likewise connected to the control computer via a control bus SWITCH CONTROL BUS. The mode of operation of this connection is such that when all the bus switches are released, the further bus switch is likewise released.

Simultaneously, via the input DISL, the lefthand bus switch Sioi is blocked in respect of the left-hand data flow direction and via the inputs DISR I and DISR 2 the right-hand bus switch Sl0l is blocked in respect of righthand directions. (An exception is formed by the bridging of arms with data sources which will be described later in the description.) In this way the data paths 101 and 112 illustrated in Fig. 11 are formed.

The illustrated bridging can be used for any bridging stage. This means that the switches S1Ol to S104 can equally constitute further bus switches of the first or a higher stage of a bridging system. In this way it is possible to construct any multi-stage bridging system.

In Fig. 12 the zone 120 framed in broken lines in Fig. 10 has been illustrated in full detail.

Here the inputs and outputs whose use is dependent upon the setting of the switch are marked with a star. When the switch is used as bus switch in a system without bridgings, all three inputs DISR 1, DISR 2 and DISL are connected to earth. With bridgings the interconnection of the four upper outputs can be gathered from Fig. 10. The same applied when the switch Sl02 is a left-hand end switch and the switch Sl03 is a right-hand end switch. The wiring of the other inputs and outputs of the two switches, thus the switches which are not marked with a star, is obvious from Fig. 12.

Fig. 13 illustrates four bus switches S12, to S,, on a data bus 125 of a computer system.

The directional switch-over is to be explained on the basis of this Figure.

Between two adjacent bus switches, an individual computer or data exchange computer is connected as the source Ql to Q2 of information to the data bus. The construction of the bus switches is as in Fig.

5, with the difference that the selection logic BCI and BC2 is replaced by a simplified, extra logic in each case provided with a driver and a resistor. The function of this simplified logic is identical to that illustrated in Fig. 7, when the inputs DISR 1 and DISR 2, DISL, DIR CTRL IN 1 and DIR CTRL in 2 are connected to '" and enable I and enable 2 are connected to "I". In Fig.

13 the input dien of BD I of each bus switch is connected to a control line DIR CTRL.

Between two adjacent connection points, a driver having an open collector output is arranged in the control line, and furthermore each of these sections can be connected via a resistor to the supply volfage. The drivers are provided with the references 131 to 134 and the resistors with the references 135 to 138. Each source possesses an output 91 92 or 93 which is connected to the control line DIR CTRL.

This output goes to "0" when the source is transmitting, i.e. when the individual computer or exchange computer is emitting data. An arrangement which is of identical construction and which is provided with a control line to which sources are connected can be additionally provided for the inputs dien of the bidirectional bus driver DB 2.

The arrangement i'llustrated in Fig. 13 realises the principle of directional switchover. This is based upon the consideration that in each bus section, there is only one transmitting source for each bus system in each exchange cycle. In the case of the control bus and address bus this can be the control computer or an exchange computer and in the case of the data bus can consist of a specific individual computer. This source transmits information to the remaining elements of a bus section; this means that the bus drivers must be connected in the direction leading away from the source.

The principle of directional switch-over is identical for both bus systems; therefore only the data bus system has been illustrated in Fig. 13. In Fig. 13 the bus driver direction is controlled via the control line DIR CTRL. If no source is transmitting, it is connected to a "1", which is effected by the resistors. As a result the drivers are connected in the right-hand direction. If a source now wishes to transmit information, it connects a "0" to the associated section of the control line. This value is communicated to the driv

Claims (1)

1. **WARNING** start of CLMS field may overlap end of DESC **.

   all three inputs DISR 1, DISR 2 and DISL are connected to earth. With bridgings the interconnection of the four upper outputs can be gathered from Fig. 10. The same applied when the switch Sl02 is a left-hand end switch and the switch Sl03 is a right-hand end switch. The wiring of the other inputs and outputs of the two switches, thus the switches which are not marked with a star, is obvious from Fig. 12.

   Fig. 13 illustrates four bus switches S12, to S,, on a data bus 125 of a computer system.

   The directional switch-over is to be explained on the basis of this Figure.

   Between two adjacent bus switches, an individual computer or data exchange computer is connected as the source Ql to Q2 of information to the data bus. The construction of the bus switches is as in Fig.

   5, with the difference that the selection logic BCI and BC2 is replaced by a simplified, extra logic in each case provided with a driver and a resistor. The function of this simplified logic is identical to that illustrated in Fig. 7, when the inputs DISR 1 and DISR 2, DISL, DIR CTRL IN 1 and DIR CTRL in 2 are connected to '" and enable I and enable 2 are connected to "I". In Fig.

   13 the input dien of BD I of each bus switch is connected to a control line DIR CTRL.

   Between two adjacent connection points, a driver having an open collector output is arranged in the control line, and furthermore each of these sections can be connected via a resistor to the supply volfage. The drivers are provided with the references 131 to 134 and the resistors with the references 135 to 138. Each source possesses an output 91 92 or 93 which is connected to the control line DIR CTRL.

   This output goes to "0" when the source is transmitting, i.e. when the individual computer or exchange computer is emitting data. An arrangement which is of identical construction and which is provided with a control line to which sources are connected can be additionally provided for the inputs dien of the bidirectional bus driver DB 2.

   The arrangement i'llustrated in Fig. 13 realises the principle of directional switchover. This is based upon the consideration that in each bus section, there is only one transmitting source for each bus system in each exchange cycle. In the case of the control bus and address bus this can be the control computer or an exchange computer and in the case of the data bus can consist of a specific individual computer. This source transmits information to the remaining elements of a bus section; this means that the bus drivers must be connected in the direction leading away from the source.

   The principle of directional switch-over is identical for both bus systems; therefore only the data bus system has been illustrated in Fig. 13. In Fig. 13 the bus driver direction is controlled via the control line DIR CTRL. If no source is transmitting, it is connected to a "1", which is effected by the resistors. As a result the drivers are connected in the right-hand direction. If a source now wishes to transmit information, it connects a "0" to the associated section of the control line. This value is communicated to the drivers arranged on the left-hand of the source and consequently said drivers reverse their direction to the left. As a result the source can emit its information in a radiating fashion.

   In the case of bridged arms of a bridging system, the source must connect such control lines DIR CTRL of the further bus switches in the same way to "0". In Fig. 14, the data flow in the case of sources within bridged sections of a briding system corresponding to Fig. 2 has been represented by way of example. The items of information emitted from the source are forwarded to a bridged section of the next higher stage via the extreme right bus switch of the bridged section to which the source is connected. The same then applies to the forwarding from stage to stage. Therefore in this case for each stage the extreme right bus driver of a section which receives information from the next lower stage is not blocked for the right-hand data flow direction even when all the bus switches in this section are released. The output DISR OUT of the bridging bus switch is inactive because its data flow direction is towards the left.

   Finally the function of the data exchange computer will be described. When the system bus has been divided into sections, these sections represent independent computer systems and require a "central" computer which undertakes the distribution of the results within the independent section. In this case it must fulfil the two following functions: I) Switching of a data path upon which data is to be transmitted 2) Transmission of data on this path.

   In principle, this can be effected by any suitably programmed computer. However, data exchange computers especially set up for this purpose have been proposed (German Offenlegungsschrift No. 26 41 741), which are also highly suitable for the computer system described here.

   WHAT WE CLAIM IS: 1. A computer system comprising a plurality of individual computers and a control computer coupled to a system bus consisting of at least two bus systems, namely an address and control bus and at least one data bus, in which: the system bus

   is divided into sections by one or more bus switches arranged therein; each bus switch possesses the characteristics that (a) the two bus systems can be interrupted under its control, (b) its transmission direction can be separately switched over for each of the bus systems, and (c) it can be directly addressed by the control computer; and one or more data exchange computers, arranged in operation to control the bus switches for the setting up of required data paths and to control the transfer of data via such paths, is/are connected to the system bus at various points.

   2. A computer system as claimed in claim 1, in which a bus switch is arranged between each two adjacent points at which an individual computer is connected to the system bus.

   3. A computer system as claimed in claim 2, in which a data exchange computer is connected at every second said point.

   4. A computer system as claimed in any one of the preceding claims, in which one or more groups, the or each of which comprises two or more adjacent bus switches on the system bus are each bridged by a further bus switch, and the or each further bus switch possesses the characteristics that (d) its transmission direction can be switched over, (e) it is enabled when all the switches within the group which it bridges are enabled and it simultaneously disables that switch within the group located at one end, and (f) it is disabled when at least one of the other switches within the group is disabled.

   5. Computer systems substantially as herein described with reference to the accompanying drawings.