JPS6350131A - Signal selecting device - Google Patents

Abstract

PURPOSE:To make it unnecessary to do something to a connecting means, even when the number of signal sources must be increased some other day, by providing a signal input disconnection detecting circuit by the number of common buses, on a selecting circuit. CONSTITUTION:As for connecting lines 3 for connecting each signal source 1, 2,-(n), and a selecting circuit 4 consisting of a deciding circuit 4A and a selector 4B, they are connected through a prescribed number (for instance, 2 pieces) of common buses B1, B2 by which each signal source 1, 2,-(n) can used in common. Therefore, when an abnormality is detected in an input clock, output stop means 10, 20-N0 having a function for stopping an output to the common buses B1, B2 of an extracted clock signal are provided on the inside of each signal source 1, 2,-(n). Also, on the pre-stage of the deciding circuit 4A of the selecting circuit 4, input disconnection detecting circuits 41, 42 for detecting the disconnection of an input signal from the common buses B1, B2 are provided.

Description

[Detailed Description of the Invention] [Summary] A plurality of signal sources that receive digital signals from external transmission paths or other devices, extract clock signals from each and output them, and clocks output from the plurality of signal sources. This relates to a signal selection device consisting of a selection circuit that receives a signal, selects and outputs one clock from among the signals, and a connection line that connects the signal source and the selection circuit. The connection line consists of at least two common buses (buses), and the selection circuit is provided with signal input disconnection detection circuits equal to the number of the common buses, so that the means for stopping the output when the signal source A signal selection device that eliminates the need to modify the connection means even when the number of signals needs to be increased.

[Industrial application field]

Time division multiplex communication equipment requires synchronization of clock signals in all devices that make up the digital network, so it is necessary to always receive clock signals from the transmission line or other devices to reliably create one mask clock. There is.

In order to improve the reliability of creating a mask clock for a time division multiplex communication device, the present invention includes a plurality of signal sources that receive digital signals from external transmission paths or other devices, extract clock signals from each, and output the extracted clock signals. A signal selection device comprising a selection circuit that receives clock signals output from the plurality of signal sources and selects and outputs one clock from among the clock signals, and a connection line that connects the signal source and the selection circuit. It is.

This type of signal selection device is not only efficient and economical at the time of initial network planning, but also suitable for signal source and selection circuits when adding signal sources as the network expands. It is desired that there is no need to modify the complicated connection means that connect the devices.

[Conventional technology]

The configuration of a conventional signal selection device is shown in FIG.

The signal selection device includes a clock extraction circuit 11 that receives a digital signal from an external transmission path or other device, extracts a clock signal from it, and outputs it, and a clock extraction circuit 11 that detects an abnormality in the transmission path or device and detects a binary value. It has a fixed number n signal sources (signal source 1 to signal source N) consisting of an abnormality detection circuit 12 that outputs a signal.

In addition to this, the signal selection device collects the detection signals output from the abnormality detection circuits 12.22 to N2 of each of the signal sources, and selects the clock output of which signal source to output as the device output. , and a selector 4B that selects and outputs one clock signal from among the output clocks of the clock extraction circuits 11.21-81 according to the selection control signal output from the judgment circuit 4A. .

[Problem that the invention seeks to solve]

In the conventional signal selection device having the above configuration, each signal source 1,
2n lines 3 are required to individually connect 2-n to the determination circuit 4A and selector 4B.

Therefore, in conventional signal selection devices, the number of signal sources and the number and location of connection destinations are limited by the number of n determined at the time of circuit design, and it is necessary to increase the number of signal sources afterward due to network expansion, etc. When this occurs, it is not easy to deal with it, and on the other hand, it is uneconomical to increase the value of n from the beginning.

[Means for solving problems]

The present invention provides each signal source 1.2...n and the determination circuit 4A.
As shown in FIG. 1, the connection line 3 that connects the selection circuit 4 consisting of
A certain number (for example, two) of common buses (
The connection is to be made via busbars B1 and B2.

Therefore, each signal source 1, 2 . ... n has an output stop means 10.20 ... NO, which has a function of stopping the output of the extracted clock signal to the common buses B1 and B2 when an abnormality is detected in the input clock. will be established.

In addition, a common bus B is provided before the determination circuit 4A of the selection circuit 4.
1. Input disconnection detection circuits 41 and 42 are provided to detect disconnection of the input signal from B2.

[Effect]

Each signal source 1, 2--n normally extracts a clock signal from the input signal by the clock extraction circuit 11 and outputs it, but the abnormality detection circuit 12, 22...N2 extracts the clock signal from the input signal and outputs it. When an abnormality is detected, the clock signal output from the clock extraction circuits 11.21-N1 is stopped by the respective output stop means 10.20...NO.

Each signal source 1.2...〇 is connected to two buses B1
, B2, but the number of signal sources that can be output simultaneously is the same as the number of buses, which is two in the case of FIG. That is, common buses B1, B2
Only one signal source outputs to each bus at the same time.

Now, the signal source 1 is normally outputting the clock to the bus B1, and the signal source 2 is normally outputting the clock to the bus B2, and the selector 4 of the selection circuit 4
Suppose that B selects the clock from bus B1 and outputs it as a device output.

When the signal source 1 detects an abnormality in the input clock by the abnormality detection circuit 12, the output control means 10 of the signal source 1 stops outputting the output clock of the clock extraction circuit 11 to the bus B1.

Input disconnection detection circuit 41 in the previous stage of the judgment circuit 4^ of the selection circuit 4
．． 42 detects that the clock input from bus B1 is cut off and that the input from bus B2 is normal, and notifies the determination circuit 4A.

The determination circuit 4A sends a determination signal to the selector 4B to stop the selection of the bus B1 whose clock input has been cut off and to select the bus B2 which is normally outputting the clock. As a result, the selector 4B outputs the clock signal from the signal source 2 as the device output, and the supply of the clock signal output is maintained.

〔Example〕

FIG. 2 is a block diagram showing the configuration of a signal selection device according to an embodiment of the present invention.

The same numbers and symbols as in the principle block diagram of FIG. 1 have the same functions. The newly provided one is driven by the output of the determination circuit 4A, and is connected to the common bus B1 to the signal sources 1.2...N.
．． An allocation control circuit 40 for allocating whether or not to output to B2 is provided, and a control bus is provided for transmitting control signals for this purpose.

The allocation control circuit 40 selects one of the n signal sources 1, 2-N according to a predetermined priority or cyclic criteria.
The number of signal sources equal to the number of common buses, in this case only two, is selected, and output permission to bus B1 or bus B2 is assigned to each of the two selected signal sources.

The control signals (data and address) for this assignment are:
It is transmitted to each signal source via a control bus, and the control register (flip-flop FFI in FIG. 3, which will be described later) of the output stop means 10 and 20 of the two signal sources.

Set the state of FF2).

FIG. 3 shows the output stop means 10.2 of the signal selection device of the present invention.
0 shows an example of the configuration of 0.

The output stopping means 10.20 of this embodiment includes two flip-flops FF1. FF2, two three-state output gates G1, G2 and one address-number circuit Ad
Consists of.

The output stop means 10.20 receives control data and address control signals from the allocation control circuit 40 via the control bus,
The control data is stored in two flip-flops FF1.FF1, which operate as control registers. The address is input to the D terminal of FF2 to the address number circuit Ad.

Two flip-flops FF1. FF2 is an address...
... Driven by the output of several circuits Ad, and a control signal is output from the Q terminal.

Control signals output from the flip-flops FFI and FP2 are respectively output from three-state output gates Gl.

G2 and turns on/off the clock output that is applied from the clock extraction circuit 11 to the buses B1 and B2 via the input gate Go.

The signal sources 1 and 2 are controlled by the output stop means 10.20 to send and stop the extracted clock signals to the buses B1 and B2, respectively.

The sent clock signal passes through buses B1 and B2,
Selector 4B of selection circuit 4 and input disconnection detection circuit 4
Entered at 1.42.

The determination circuit 4A controls the selector 4B to select the bus that is normally supplying the clock signal based on the outputs of the input disconnection detection circuits 41 and 42.

Bus B1. When an input interruption is detected in one of B2, the determination circuit 4A switches the selector 4B and notifies the allocation control circuit 40 of the abnormality of the signal source.

The allocation control circuit 40 sends a control signal conveying this abnormality to the signal source 1.2-N via the control bus, and output stop means 10.20 for the abnormal signal source so as to disconnect the abnormal signal source from the bus. Set the control register for... At the same time, use of the vacant bus is newly assigned to another signal source, and the control register of that signal source is set so that the bus can be used.

To Mr. Kono, 2 tsu (D lotus B1. B2 is the signal at, 2
-N, a signal selection device is configured that is not limited by the number of signal sources.

〔Effect of the invention〕

As explained above, according to the present invention, a signal selection device is configured that is not limited by the signal source, so even when the network is expanded after the plan and the number of signal sources is increased beyond the plan, the signal selection device is not limited by the signal source. This has the effect that it can be handled without modifying the connection line that connects the source and the selection circuit.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram showing the configuration of a signal selection device according to the present invention, FIG. 2 is a block diagram showing the configuration of a signal selection device according to an embodiment of the present invention, and FIG. 3 is a block diagram showing the operation of an embodiment of the present invention. FIG. 4 is a block diagram showing the configuration of a conventional signal selection device. 1, 2, and 4, 1.2...n is a signal source, 10.20 is an output stop means 11.21 is a clock extraction circuit, 12.22 is an abnormality detection circuit, and 3 is a connection. 4 is a selection circuit, 40 is an allocation control circuit, 41.42 is an input disconnection detection circuit, 4A is a determination circuit, and 4B is a selector. $3g

Claims (1)

[Claims] A plurality of signal sources (1, 2...n) that extract and output clock signals from digital signal input, and a plurality of signal sources (1, 2...n) that extract and output clock signals from digital signal inputs. - A connection line (3) that transmits the signal output of n), and a selection circuit (4) that determines whether the clock signal transmitted by the connection line (3) is normal or abnormal and selects and outputs one clock signal. In a signal selection device consisting of The selection circuit (4) consists of at least two common buses, and the selection circuit (4) includes a circuit (41) for detecting disconnection of the input signal.
, 42) as many as the common buses.