JPH0125096B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a computer system in which each individual computer in a group has at least two bus systems, namely an address and control bus;
The present invention relates to a computer system that can be coupled to a control computer via a system bus consisting of a data bus.

A computer system of this type is known (West German Patent Application No. 2546202). In this computer system, the control computer distributes data as follows. That is, each control computer sequentially supplies the results of one individual computer's operation to the system bus and writes them into the remaining individual computers, regardless of how many individual computers require the results. . Therefore, exchange cycles equal to the operating results to be distributed for the entire data exchange are required.

The efficiency of the computer system of the type mentioned at the beginning is
This is largely related to the time required for information exchange between individual computers. The aim here is to obtain the shortest exchange times possible.

In many problems to be solved, only limited neighbor-joining, ie, information exchange between adjacent elementary tasks, is required. For handling in computer systems of the type mentioned at the outset, it is important that exchanges are only necessary between individual computers arranged at limited intervals from one another.
The limited neighbor coupling between individual computers in a computer system is known to the field computer (e.g. GH
Barnes, R.M.Brown, M.Kato, DJKuck, D.
(See L. Slotnick, RA Stokes, “ILLIAC Fourth Computer,” IEEE Trans.on Comp., Volume C-17, Volume 8, August 1968). Here each individual computer is tightly coupled to each other, ie each individual computer is coupled to four neighboring computers. However, this tight bond is only advantageous in cases of poor fit. Problems where the combination does not match the computer configuration, such as in the case of higher-order supplies or irregular combinations, make the data exchange significantly more complicated and slow, thus requiring longer exchange times. It becomes like this.

An object of the present invention is to provide a computer system of the type mentioned at the beginning, which can utilize limited neighbor coupling to shorten the exchange phase. To achieve this object, according to the present invention, a control computer is connected to one end of a system bus consisting of an address bus, a data bus, and a control bus, and a plurality of bus switches are arranged in series on the system bus, and each bus switch In a computer system in which individual computers are connected between the two computers, the bus switch includes circuit means for disconnecting the address bus and the data bus according to instructions from each individual computer or control computer;
The control system consists of a signal transmission circuit means connected to the control line of the control bus and outputs a signal to the next stage bus, and a circuit means for changing the data flow direction of the address bus and data bus according to the signal from the signal transmission circuit means. The control line of the bus is connected at one end to the control computer, connects the signal transmission circuit means of each bus switch in series, and is connected to each computer between each bus switch, thereby allowing data on the data bus and address bus to be connected to the control computer. A signal that specifies the data distribution direction is transmitted in one direction from the control computer side (upstream) to each bus switch side (downstream), and the control computer outputs a first level signal that specifies the data distribution direction to the control line, One of the individual computers that performs data transmission outputs a second level signal that defines the data flow direction to the control line, and this causes the flow direction of the bus switch downstream from the individual computer to change to the first level. 2nd from the direction indicated by the level
Therefore, the data output from each computer to the address bus and data bus is transmitted radially.

With this computer system, for problems with fixed or irregular connections, all bus switches can be closed and results can be exchanged between all individual computers. For problems with limited proximity coupling, the system bus can be divided into many sections by interrupting bus switches, within which data exchanges are performed simultaneously and independently of each other, each controlled by a data exchange computer. can be done.

Due to this parallel exchange, the exchange time can be significantly reduced in many problems.

An advantageous embodiment of the invention provides for a bus switch to be arranged on the system bus between two adjacent connection points of each individual computer.

A further advantageous embodiment is characterized in that at each second connection point a respective data exchange computer is connected.

Next, the present invention will be described with reference to illustrated embodiments.

Fig. 1 is a diagram of the computer configuration; Fig. 2 is a two-dimensional grid; Fig. 3 is a linear diagram; Fig. 4 is an example of a bus switch or other bus switch;
5 shows an embodiment of the two-branch bus driver, FIG. 6 shows the control logic for the bus switch in FIG. 4, FIG. 7 shows the selection logic for the bus switch in FIG. 4, and FIG. 8 shows the release logic for the bus switch in FIG. 4. , FIG. 9 shows an embodiment for the wiring of adjacent bus switches, and FIG. 10 shows an embodiment for the principle of direction switching.

In Figure 1, system bus 1 has locations m ₁ to _{m 6}
, each of the computers M ₁ to M ₆ is connected.
A bus switch S _i is arranged in the system bus between two adjacent connection points m _i and m _i+1 respectively. There are therefore five bus switches S ₁ to S ₅ . The system bus is divided into sections _a1 to _a6 by the bus switch. Furthermore, data exchange computers ATR ₁ , ATR ₂ , and ATR ₃ are connected.
The left side of the system bus opens to the control computer STR. The system can be thought of as moving toward the right. In particular, such a computer system is constituted by a microprocessor module.

Before going into the explanation of the specific configuration of the computer system shown in Figure 1, let us explain how the exchange width is adapted to the combined width of the problem being processed in the computer configuration shown in Figures 2 and 3. Show what you get. In this case, the influence of the combining method on the data exchange time will be considered for one example. As an example, a two-dimensional problem structure is used as the basis, as shown in Figure 2. Such a structure appears when solving partial differential equations by the method of constant differentiation, and is applied, for example, to electric field calculations or weather forecasting. In this case data exchange is only necessary between immediately adjacent grid points. The example of halftone dot i is highlighted in FIG. 2, and this halftone dot exchanges data only with its four immediate neighbors i-1, i-n, i+1, and i+n. The problem is illustrated in the linear computer structure shown here. For example, by illustrating with FIG. 1 where each computer handles one grid dot, it is possible to make it necessary to exchange data only within a predetermined bandwidth. The results from each computer belonging to grid point i are
It must be given to each computer distributed in n, i-1, i+1, i+n. That is, the band width is 2n+1. Figure 3 shows a situation projected in one dimension.

The computer system according to the invention advantageously adapts to this problem by dividing the system bus into sections of length 2n+1. A bus switch is useful for division.
Within these intervals, the results of each central computer are distributed. In the next step the system bus section is shifted by one bus switch,
The results are now distributed to each computer in the middle of the interval, and so on. Since they are exchanged simultaneously in the entire interval, in order to distribute the n ² results, 2
Only 1 n+1 exchange steps are required.
A reduction in the data exchange phase is thus provided by a factor equal to the ratio of the grid dots/bandwidth of the group. Where the number of grid points is ¹⁰⁴ and the band width is 201, n =
In a two-dimensional problem with 100, the number of exchange steps is reduced by approximately 1/50 of the number of grid dots.
It should be pointed out that the computer system of this invention is not limited to this example, but can be applied to other problem structures as well.

FIG. 4 shows a particularly advantageous embodiment of the bus switch. This embodiment is configured in such a way that it can be used simultaneously as another bus switch. According to Figure 4, the bus switch selects logic SSL,
Release logic SEL, two bifurcated bus drivers BD1 or BD2 connected in the system bus,
It consists of an associated control logic BC1 or BC2 and an operation mode changeover switch S, in which case the above
BD1 is connected to the data bus, and BD2 is connected to the address bus. A changeover between two operating modes is possible via an operating mode changeover switch S, whereby in one operating mode (called A) the bus switch state is determined by the release logic SEL, i.e. by the control computer. Addressed and controlled. In the other mode of operation (referred to as B), the operating state is established via the ENABLE input, which can be connected to the ENABLED output of another bus switch configured in the same way, so that the bus switch can can assume the operational status of things.

Between the ENABLED output and the operation mode switch S,
A driver 50 with an open collector output is still connected, which is useful for many bus switches.
ENABLED Allows hard-wired AND combinations of outputs.

FIG. 5 shows two identically constructed bidirectional bus drivers BD1 or BD2. These are two 4-bit parallel two-branch bus drivers SAB82.
deals with bus drivers for bit-parallel transmission of 1 byte consisting of 16 bits (Siemens Corporation, 1976/77 "Databook" system SAB)
8080 microprocessor device).
Here, and in the following, the inputs and outputs of the elements are labeled as in the above document. Through the common input and the inputs of both connected elements,
Bus drivers can be blocked. The direction of data flow is determined via the inputs grouped into a common input of the bus driver. Details are given in the above reference. The terminals DI, DO or DB represent the inputs DI ₀ to DI ₃ , DO ₀ to DO ₃ or DB ₀ to DB ₃ of the document.

FIG. 6 shows the structure of control logic BC1 or BC2 in detail. Element 7408 for three AND circuits 81, 82, 83 each having two inputs;
Element 7427 and inverter 8 for OR circuit 84
For the NAND circuit 87 having three inputs, the element 7404 is suitable for the NAND circuit 87 having three inputs, and the Siemens open collector element 7422 is suitable for the NAND circuit 87 having three inputs.
(See “Digital Connections” in the databook above). Input DIR Input connected to CTRL1 or 2
The former direction can be determined via DIR CTRLIN1. This input is connected to the inverter 85 on the one hand.
is connected to the inputs of the NAND circuit 87 and the AND circuit 81, and directly connected to the respective inputs of the AND circuit 83 on the other hand. Therefore, the output 7 connected to the input of the attached two-branch bus driver
There is a direct connection of the above input with 02. input
enable1 or enable2 is the output 53 of the operation mode switcher on the one hand, and the second output of the AND circuit 83 on the other hand.
It is connected to the input and the second input of the circuit 87, and is invertedly connected to the input of the OR circuit 84. The main problem with input enable 1 is that on the one hand the OR circuit 8
4 outputs and a 2-branch bus driver on the other hand
The purpose is to block or free the bus driver via the output 701 to be connected to the input of BD1 or BD2. When the corresponding bus driver is freed via input enable 1 or 2 of the control logic BC1, BC2, the direction information can be relayed to the next bus switch. Enter this information
Through DIR CTRL IN1 or 2 (see Figure 4),
Given to bus switch. Control logic input
DISL is connected to the second input of the AND circuit 82,
Input DISR1 or 2 is connected to the input of AND circuit 81. The output of these AND circuits is OR circuit 8
It is connected to the second or third input of 4. One input of the AND circuit 82 is connected to a third input of a NAND circuit 87 via an inverter 86, and a second input of the AND circuit 82 is connected to a first input of the NAND circuit. Bus driver BD1 or 2 is the input
Via DISR1 or 2 or DISL, data flow direction to the right or left can be selectively blocked. The output of the AND circuit 83 forms the output DISR OUT1 or 2 of the bus switch. Noah circuit 8
The output of 7 is the bus switch output DIR CTRL
Forms OUT1 or 2.

FIG. 7 shows the switch selection logic SSL in detail. Two 4-bit comparators 81, 82 in parallel
(Element 7485 on pages 123 and 124 of "Digital Connections" above) is used. Comparator 82 shown there
input 2 (A<B), 3 (A=B) or 4 (A>
B) is the corresponding output 7 of comparator 81 (A<B),
6 (A=B) or 5 (A>B) in parallel. The 4-bit terminal A or B corresponds to the terminals A ₀ to A ₃ or B ₀ to B ₃ in the above-mentioned document. Terminals A of both comparators 81, 82 form byte terminals to be connected to the address bus. The 4-bit terminals B of both comparators are connected in parallel to an 8-fold coder switch 83 having a pull-up resistor. Input 3 (A=B) of comparator 81 is connected to logic “1” through resistor 84.
The output 6 (A=B) of the comparator 82 is connected to the input of the selected release logic SEL. With the diagrammatically shown coder switch 83, the bus switch can be provided with a fixed switch number. Input A
If the number given through matches the switch number, output 6 (A=B) is set to logic "1".

Figure 8 shows the release logic SEL in detail. These are four OR circuits 91 to 94, each with two inputs, and an AND circuit 9, each with three inputs.
5, 96, a D flip-flop 97 and an inverter 98. The selected input is connected to the input of the OR circuit 91 via an inverter 98.
The output of this OR circuit is connected on the one hand to the respective inputs of AND circuits 95 and 96.
The output of the AND circuit 95 is a D flip-flop 97.
The input D of and the output of the AND circuit 96 are input T(9
7 is element 7474 of the above-mentioned document "Digital Connection" pages 190-191, and is connected to the element 7474 (using the same symbols as its input and output). The input R of this flip-flop is connected to the input of the bus switch. The input S of the flip-flop is continuously placed at logic "1". The output Q is connected to the input of the OR circuit 94 and the outputs EN RIGHT OUT and EN LEFT OUT of the bus switch (see FIG. 4).
The output of the OR circuit 94 forms the output of the release logic, which output is connected to the input 51 of the operating mode switch, the other input 52 of which is connected to the input of the bus switch. Bus switch input
SHIFT is on the other hand AND circuit 96
and the input of the OR circuit 93. Similar to bus switch input
LEFT is connected to the third input of the AND circuit 96 and the input of the OR circuit 92. The input is the second input of the OR circuit 94 and the input
SELECT is the second input of the OR circuit 91,
Thus, the input EN LEFT IN is connected to the second input of the OR circuit 92. The output of the OR circuit 92 is connected to the second input of the AND circuit 95, and the output of the OR circuit 93 is connected to the third input of the same. The D flip-flop, which serves as the marking flip-flop, is set by three different signals: when selecting the bus switch (selecting "1"), a pulse to the bus switch causes this flip-flop to go to logic "0"; is set,
That is, the output Q is at "0".
A pulse to LEFT causes the flip-flop to be charged by the state of the input EN LEFT IN,
During SHIFT pulse, OR circuit 93
It is charged depending on the input of SHIFT RIGHT IN and the state of the connected input SHIFT RIGHT IN. SHIFT mentioned here
Advantageous connection by LEFT or SHIFT RIGHT is
Easy shifting of bus sections once divided,
By applying a pulse to SHIFT or , the computer system can be applied particularly advantageously to problem structures such as those described in FIGS. 2 and 3.

Input S is logic “0”
, the current binary value at the output Q of the flip-flop is present at the output of the logic. At that time, when the output is placed at “0”,
The bus switch is shut off. In other cases, the switch is opened. input
If MODE is placed at logic "1", the output will also be at this value, which means the bus switch is closed. It is therefore possible to switch between a segmented system bus and a direct system bus without significant time loss.
Via the input, the marking flip-flop can be reset to the basic state Q="1". The significance of the marking flip-flop is then as follows: the bus switch is "marked", which is the "selection mode" of the operating mode.
should be interrupted when This marking can be done in three ways as described above. However, the bus switch inputs
If "1" is applied to , it remains closed. Information is thereby sent from the control computer to all computers, data exchange computers and bus switches present in the system. Therefore, the order of marking the bus switches is arbitrary. If, on the other hand, the bus switch were to be shut off immediately, all elements present behind this switch would no longer be able to be reacted by the control computer. That is, first of all, the bus switch present on the trailing path must be shut off. input
If SELECTION is set to “0”,
The system bus is disconnected at the marked point.

During data exchange via a divided system bus, access from the control computer to all or some of the components present on the trailing path may be temporarily short-circuited, for example to change the program in the data exchange computer. It takes time. Therefore, it was divided
A time-saving switching between a system bus and a directly connected system bus can be realized in a simple manner with the aid of flip-flops.

FIG. 9 shows the connection relationship between adjacent bus switches. Inputs and outputs are marked with small stars. 3
All inputs DISR1, DISR2 and DISL are grounded.
The same holds true if switch S ₁₀₂ is the left-most switch or switch S ₁₀₃ is the right-most switch. The remaining inputs and outputs of both switches, ie, the connections of the inputs and outputs not marked with small stars, are given naturally from FIG.

Figure 10 shows the data bus 12 of the computer system.
5, four bus switches S ₁₂₁ to S ₁₂₄ are shown.
Direction switching will be explained with reference to this diagram. Between two adjacent bus switches, each information source Q ₁
Each computer or data exchange computer is connected to the data bus as _Q3 . The bus switch is constructed as shown in FIG. 4, except that the control logic BC1 or BC2 is replaced by a simplified specially shown logic having a driver and a resistor, respectively. The operation of this simplified logic is that when input DISR1 or 2, DISL DIR CTRL IN1 or 2 in FIG. This is consistent with the logic in Figure 6. Between two adjacent connection points in each case, a driver with an open collector output is arranged in the control line DIR CTRL, and each of these paths can furthermore be connected to the supply voltage via a resistor. Driver is reference number 13
1 to 134, and the resistors have reference numerals 135 to 138. Each source has an output of 91, 92 or 93
, which is connected to the control line DIR CTRL.
This output is transmitted when the source transmits, i.e. when each individual computer or switching computer sends out data.
Set to “0”. For the two-way bus driver BD2, an additional identically designed device is provided with a control line to which a power source can be connected.

The device of FIG. 10 realizes the principle of direction switching, starting from the following interpretation. Only one transmitting source is provided for each bus system in each switching cycle on each bus section. This source can be a control computer or a switching computer for the control and address buses, and a predetermined individual computer for the data bus. These sources transmit information to the remaining elements of the bus section, which means that the bus drivers must be connected in the direction of the sources.

The principle of direction switching is the same for both bus systems; therefore only the data bus system is shown in FIG. The bus driver direction is controlled via the control line DIR CTRL according to FIG. If there is no transmission from any source, the source is at "1" and this is done by the resistor. This connects the driver in the right direction. When a source sends information,
Apply "0" to the relevant section of the control line. This value is signaled to the driver located to the left of the source, thereby causing the driver to reverse its direction to the left. This allows the source to transmit its information radially.

Next, the functions of the data exchange computer will be explained. When the system bus is divided into sections, this section automatically becomes the computer system, and thus the "center" where the automatic distribution of results within the section takes place.
A calculator is required. In this case, the following two issues should be satisfied.

(1) Connection of the data path along which the data is to be transmitted; (2) Transmission of the data via this path. In principle, this can be done by a suitably programmed computer. However, data exchange computers designated for this purpose have already been proposed and are also suitable for the computer system of the invention.

[Brief explanation of drawings]

Fig. 1 is a diagram of the computer configuration, Fig. 2 is a two-dimensional grid network, Fig. 3 is a linear diagram, Fig. 4 is an example of a bus switch or other bus switch, and Fig. 5 is an example of a two-branch bus driver. Embodiment, FIG. 6 shows the control logic for the bus switch in FIG. 4, FIG. 7 shows the selection logic for the bus switch in FIG. 4, and FIG. 8 shows the control logic for the bus switch in FIG.
The figure shows the release logic for the bus switch of FIG. 4, FIG. 9 shows an embodiment for the connection of adjacent bus switches, and FIG. 10 shows an embodiment for the principle of direction switching. 1, 2...System bus, 81, 82...4-bit comparator, 83...8-fold coder switch, 97
...D flip-flop, a ₁ to a ₆ ... section,
ATR ₁ ~ _{ATR 3} ……Data exchange computer, BC1,
BC2...Control logic, BD1, BD2...Bus driver, _M1 to _M6 ...Each computer, _Q1 to _Q3 ...
...Data source, S...Operation mode changeover switch, S ₁ ~
S ₂₀ ... bus switch, S ₁₀₁ - S ₁₀₄ , S ₁₂₁ - _{S 124} ...
…Bus switch, SEL…Release logic, SSL…
...Selection logic, STR...Control computer.

Claims (1)

[Claims] 1. A computer system in which a control computer is connected to one end of a system bus consisting of an address bus, a data bus, and a control bus, a plurality of bus switches are arranged in series with the system bus, and each computer is connected between each bus switch. In the above, the bus switch includes circuit means for disconnecting the address bus and data bus according to instructions from each computer or control computer, and a signal transmission circuit connected to the control line (DIR CTRL) of the control bus and outputting a signal to the next stage bus. circuit means for changing the data flow direction of the address bus and the data bus in response to a signal from the signal transmission circuit means;
CTRL) is connected to a control computer at one end, connects the signal transmission circuit means of each bus switch in series, and is connected to each computer between each bus switch, thereby distributing data on the data bus and address bus. A signal specifying the direction is transmitted in one direction from the control computer side (upstream) to each bus switch side (downstream), and the control computer outputs a first level (1) signal specifying the data distribution direction to the control line. , 1 of each computer that transmits data
Each computer in the machine has a second
outputs a level (0) signal to the control line, thereby changing the flow direction of the bus switch downstream from the respective computer from the direction specified by the first level to the direction specified by the second level. A computer system characterized in that data output from each computer to an address bus and a data bus is transmitted radially.