CA1030665A - Partial planarization of electrically insulative films by resputtering - Google Patents
Partial planarization of electrically insulative films by resputteringInfo
- Publication number
- CA1030665A CA1030665A CA202,290A CA202290A CA1030665A CA 1030665 A CA1030665 A CA 1030665A CA 202290 A CA202290 A CA 202290A CA 1030665 A CA1030665 A CA 1030665A
- Authority
- CA
- Canada
- Prior art keywords
- resputtering
- electrically insulative
- insulative films
- partial planarization
- planarization
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Composite Materials (AREA)
- Materials Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA298,325A CA1044378A (en) | 1973-06-29 | 1978-03-20 | Partial planarization of electrically insulative films by resputtering |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US00375298A US3804738A (en) | 1973-06-29 | 1973-06-29 | Partial planarization of electrically insulative films by resputtering |
Publications (1)
Publication Number | Publication Date |
---|---|
CA1030665A true CA1030665A (en) | 1978-05-02 |
Family
ID=23480308
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA202,290A Expired CA1030665A (en) | 1973-06-29 | 1974-06-12 | Partial planarization of electrically insulative films by resputtering |
Country Status (7)
Country | Link |
---|---|
US (1) | US3804738A (it) |
JP (2) | JPS5546060B2 (it) |
CA (1) | CA1030665A (it) |
DE (1) | DE2430692C2 (it) |
FR (1) | FR2235481B1 (it) |
GB (1) | GB1418278A (it) |
IT (1) | IT1010165B (it) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5639020B2 (it) * | 1973-10-05 | 1981-09-10 | ||
US3976524A (en) * | 1974-06-17 | 1976-08-24 | Ibm Corporation | Planarization of integrated circuit surfaces through selective photoresist masking |
US4036723A (en) * | 1975-08-21 | 1977-07-19 | International Business Machines Corporation | RF bias sputtering method for producing insulating films free of surface irregularities |
US4007103A (en) * | 1975-10-14 | 1977-02-08 | Ibm Corporation | Planarizing insulative layers by resputtering |
DD136670A1 (de) * | 1976-02-04 | 1979-07-18 | Rudolf Sacher | Verfahren und vorrichtung zur herstellung von halbleiterstrukturen |
US4035276A (en) * | 1976-04-29 | 1977-07-12 | Ibm Corporation | Making coplanar layers of thin films |
US4029562A (en) * | 1976-04-29 | 1977-06-14 | Ibm Corporation | Forming feedthrough connections for multi-level interconnections metallurgy systems |
FR2375718A1 (fr) * | 1976-12-27 | 1978-07-21 | Radiotechnique Compelec | Dispositif semiconducteur a reseau d'interconnexions multicouche |
DE2705611A1 (de) * | 1977-02-10 | 1978-08-17 | Siemens Ag | Verfahren zum bedecken einer auf einem substrat befindlichen ersten schicht oder schichtenfolge mit einer weiteren zweiten schicht durch aufsputtern |
NL7701559A (nl) * | 1977-02-15 | 1978-08-17 | Philips Nv | Het maken van schuine hellingen aan metaal- patronen, alsmede substraat voor een geinte- greerde schakeling voorzien van een dergelijk patroon. |
US4111775A (en) * | 1977-07-08 | 1978-09-05 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Multilevel metallization method for fabricating a metal oxide semiconductor device |
JPS5432091A (en) * | 1977-08-15 | 1979-03-09 | Nec Corp | Radar interference eleimenating system |
JPS597212B2 (ja) * | 1977-09-05 | 1984-02-17 | 富士通株式会社 | プラズマ・エッチング方法 |
US4289834A (en) * | 1977-10-20 | 1981-09-15 | Ibm Corporation | Dense dry etched multi-level metallurgy with non-overlapped vias |
US4172004A (en) * | 1977-10-20 | 1979-10-23 | International Business Machines Corporation | Method for forming dense dry etched multi-level metallurgy with non-overlapped vias |
JPS54159662A (en) * | 1978-06-07 | 1979-12-17 | Hitachi Ltd | Method of connecting wire conductors |
US4492717A (en) * | 1981-07-27 | 1985-01-08 | International Business Machines Corporation | Method for forming a planarized integrated circuit |
JPS5893354A (ja) * | 1981-11-30 | 1983-06-03 | Mitsubishi Electric Corp | 半導体装置の製造法 |
US4396458A (en) * | 1981-12-21 | 1983-08-02 | International Business Machines Corporation | Method for forming planar metal/insulator structures |
JPS59200440A (ja) * | 1983-04-28 | 1984-11-13 | Agency Of Ind Science & Technol | 配線構造の製造方法 |
US4470874A (en) * | 1983-12-15 | 1984-09-11 | International Business Machines Corporation | Planarization of multi-level interconnected metallization system |
JPH0618194B2 (ja) * | 1984-07-21 | 1994-03-09 | 工業技術院長 | 段差の被覆方法 |
JPH0697660B2 (ja) * | 1985-03-23 | 1994-11-30 | 日本電信電話株式会社 | 薄膜形成方法 |
US4756810A (en) * | 1986-12-04 | 1988-07-12 | Machine Technology, Inc. | Deposition and planarizing methods and apparatus |
US5256594A (en) * | 1989-06-16 | 1993-10-26 | Intel Corporation | Masking technique for depositing gallium arsenide on silicon |
US5855966A (en) * | 1997-11-26 | 1999-01-05 | Eastman Kodak Company | Method for precision polishing non-planar, aspherical surfaces |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3514844A (en) * | 1967-12-26 | 1970-06-02 | Hughes Aircraft Co | Method of making field-effect device with insulated gate |
US3549876A (en) * | 1968-03-07 | 1970-12-22 | Eaton Yale & Towne | Crane operating radius indicator |
FR2119930B1 (it) * | 1970-12-31 | 1974-08-19 | Ibm | |
DE2202077A1 (de) * | 1971-05-17 | 1972-11-30 | Hochvakuum Dresden Veb | Verfahren zur Herstellung von Mehrlagenleiterplatten |
-
1973
- 1973-06-29 US US00375298A patent/US3804738A/en not_active Expired - Lifetime
-
1974
- 1974-04-29 IT IT21996/74A patent/IT1010165B/it active
- 1974-04-29 FR FR7415815A patent/FR2235481B1/fr not_active Expired
- 1974-05-17 JP JP5462574A patent/JPS5546060B2/ja not_active Expired
- 1974-05-17 GB GB2223074A patent/GB1418278A/en not_active Expired
- 1974-06-12 CA CA202,290A patent/CA1030665A/en not_active Expired
- 1974-06-26 DE DE2430692A patent/DE2430692C2/de not_active Expired
-
1980
- 1980-03-17 JP JP3279580A patent/JPS55130147A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
FR2235481A1 (it) | 1975-01-24 |
GB1418278A (en) | 1975-12-17 |
JPS5623302B2 (it) | 1981-05-30 |
DE2430692C2 (de) | 1982-10-21 |
JPS5546060B2 (it) | 1980-11-21 |
JPS55130147A (en) | 1980-10-08 |
IT1010165B (it) | 1977-01-10 |
FR2235481B1 (it) | 1976-07-16 |
DE2430692A1 (de) | 1975-01-16 |
US3804738A (en) | 1974-04-16 |
JPS5024079A (it) | 1975-03-14 |
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