BR9815918A - Instalação eletrônica de memória - Google Patents

Instalação eletrônica de memória

Info

Publication number
BR9815918A
BR9815918A BR9815918-6A BR9815918A BR9815918A BR 9815918 A BR9815918 A BR 9815918A BR 9815918 A BR9815918 A BR 9815918A BR 9815918 A BR9815918 A BR 9815918A
Authority
BR
Brazil
Prior art keywords
programming voltage
electronic memory
memory cells
memory installation
test mode
Prior art date
Application number
BR9815918-6A
Other languages
English (en)
Inventor
Heiko Fibranz
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of BR9815918A publication Critical patent/BR9815918A/pt

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46—Test trigger logic

Landscapes

  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

Patente de Invenção: <B>"INSTALAçãO ELETRôNICA DE MEMóRIA"<D>. Descreve-se uma instalação eletrônica de memória (1), com células de memória programáveis eletricamente, um barramento de endereço (30) para o endereçamento das células de memória, assim como uma bomba controlável de tensão de programação (22) para a geração de uma tensão de programação para as células de memória, instalação de memória esta que se caracteriza por uma unidade de conexão (23) que pode ser acionada com um sinal de modo de teste e pela qual o barramento de endereço (30) em um modo de teste pode ser ligado á bomba de tensão de programação (22) de um modo tal que, por meio de bits de endereço fornecidos seja possível ajustar uma tensão predeterminável de programação de teste.
BR9815918-6A 1998-06-24 1998-06-24 Instalação eletrônica de memória BR9815918A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/DE1998/001738 WO1999067791A1 (de) 1998-06-24 1998-06-24 Elektronische prüfungsspeichereinrichtung

Publications (1)

Publication Number Publication Date
BR9815918A true BR9815918A (pt) 2001-02-20

Family

ID=6918657

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9815918-6A BR9815918A (pt) 1998-06-24 1998-06-24 Instalação eletrônica de memória

Country Status (12)

Country Link
US (1) US6366510B2 (pt)
EP (1) EP1088311B1 (pt)
JP (1) JP2002532813A (pt)
KR (1) KR20010053128A (pt)
CN (1) CN1127090C (pt)
AT (1) ATE218004T1 (pt)
BR (1) BR9815918A (pt)
DE (1) DE59804216D1 (pt)
MX (1) MXPA00012846A (pt)
RU (1) RU2216796C2 (pt)
UA (1) UA52828C2 (pt)
WO (1) WO1999067791A1 (pt)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7073094B1 (en) * 2002-05-09 2006-07-04 Winbond Electronics Corporation Method and systems for programming and testing an embedded system
JP2004110871A (ja) * 2002-09-13 2004-04-08 Fujitsu Ltd 不揮発性半導体記憶装置
US20050036947A1 (en) * 2003-08-12 2005-02-17 General Electric Company Target-specific activatable polymeric imaging agents
JP2005071556A (ja) * 2003-08-28 2005-03-17 Renesas Technology Corp 半導体記憶装置および半導体集積回路装置
US10261876B2 (en) 2016-11-08 2019-04-16 Micron Technology, Inc. Memory management

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5177745A (en) * 1990-09-26 1993-01-05 Intel Corporation Memory device with a test mode
US5291446A (en) 1992-10-22 1994-03-01 Advanced Micro Devices, Inc. VPP power supply having a regulator circuit for controlling a regulated positive potential
JP3331481B2 (ja) * 1993-07-14 2002-10-07 日本テキサス・インスツルメンツ株式会社 半導体装置の試験回路
US5606532A (en) * 1995-03-17 1997-02-25 Atmel Corporation EEPROM array with flash-like core
US5615159A (en) * 1995-11-28 1997-03-25 Micron Quantum Devices, Inc. Memory system with non-volatile data storage unit and method of initializing same
KR0185611B1 (ko) * 1995-12-11 1999-04-15 김광호 불휘발성 반도체 메모리장치의 고전압 레벨 최적화 회로 및 그 방법
US5650734A (en) * 1995-12-11 1997-07-22 Altera Corporation Programming programmable transistor devices using state machines
US6154851A (en) * 1997-08-05 2000-11-28 Micron Technology, Inc. Memory repair

Also Published As

Publication number Publication date
RU2216796C2 (ru) 2003-11-20
EP1088311A1 (de) 2001-04-04
MXPA00012846A (es) 2002-06-04
EP1088311B1 (de) 2002-05-22
UA52828C2 (uk) 2003-01-15
WO1999067791A1 (de) 1999-12-29
KR20010053128A (ko) 2001-06-25
US6366510B2 (en) 2002-04-02
CN1127090C (zh) 2003-11-05
US20010002887A1 (en) 2001-06-07
ATE218004T1 (de) 2002-06-15
DE59804216D1 (de) 2002-06-27
JP2002532813A (ja) 2002-10-02
CN1310847A (zh) 2001-08-29

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 7,8 E 9A ANUIDADES

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 1910 DE 14/08/2007.