US20010002887A1 - Electronic memory device - Google Patents
Electronic memory device Download PDFInfo
- Publication number
- US20010002887A1 US20010002887A1 US09/748,473 US74847300A US2001002887A1 US 20010002887 A1 US20010002887 A1 US 20010002887A1 US 74847300 A US74847300 A US 74847300A US 2001002887 A1 US2001002887 A1 US 2001002887A1
- Authority
- US
- United States
- Prior art keywords
- programming voltage
- memory device
- memory cells
- test
- electronic memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/46—Test trigger logic
Definitions
- the switching device is a multiplexer.
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
An electronic memory device (1) having electrically programmable memory cells, an address bus (30) for addressing the memory cells, and also a controllable programming voltage pump (22) for producing a programming voltage for the memory cells. The electronic memory device is distinguished by a switching device (23) which can be actuated by a test mode signal and which can be used to connect the address bus (30) to the programming voltage pump (22) in a test mode such that a prescribable test programming voltage can be set using supplied address bits.
Description
- This is a continuation of copending international application PCT/DE98/01738, filed Jun. 24, 1998, which designated the United States.
- The invention relates to an electronic memory device having electrically programmable memory cells, an address bus for addressing the memory cells, and a controllable programming voltage pump for producing a programming voltage for the memory cells.
- Electronic memory devices of this kind are generally produced on a semiconductor chip containing, for example, an EEPROM module (Electrically Erasable Programmable Read-Only Memory) having an EEPROM array and a programmable voltage pump, and also a further module which has decoding and logic circuits and to which the inputs and outputs of the chip are connected. In this context, the memory array represents the actual memory and includes a configuration made up of a plurality of memory cells.
- To program the individual EEPROM memory cells, a programming voltage of, for example, 20 V needs to be applied to them, where the programming voltage is much higher than the supply voltage of, for example, 5 V. The optimum programming voltage is obtained on the chip from the supply voltage using the regulated voltage pump.
- EP-A 0 594 294 has disclosed an electronic memory device which has electrically programmable memory cells, an address bus for addressing the memory cells and also a controllable programming voltage pump for producing a programming voltage for the memory cells.
- After such a semiconductor chip has been manufactured, the EEPROM needs, amongst other things, to be tested for its operability. For this, special programming commands used to program the memory array are provided.
- In one of these tests, the programming voltage is lowered to a particular value, for example, in order to check whether the memory cells are just short of being reprogrammed at this programming voltage.
- This programming voltage is supplied to the semiconductor chip externally via an additional test pad. This test pad is not required for normal operation of the memory device, however, and takes up chip area which is not available for enlarging the storage capacity, or makes the chip larger than it would actually need to be.
- It is accordingly an object of the invention to provide an electronic memory device of the type mentioned in the introduction in which the aforementioned test pad is not necessary for carrying out the operational test on the memory.
- With the foregoing and other objects in view there is provided, in accordance with the invention an electronic memory device including electrically programmable memory cells; an address bus for addressing the memory cells; a controllable programming voltage pump for producing a programming voltage for the memory cells; and a switching device configured for actuation in a test mode by a test mode signal and for connecting the address bus to the programming voltage pump in the test mode such that the programming voltage can be set to a predetermined test programming voltage using address bits supplied on the address bus.
- In particular, the electronic memory device mentioned in the introduction is provided with a switching device which can be actuated by means of a test mode signal and can be used to connect the address bus to the programming voltage pump in a test mode such that a predetermined or prescribable test programming voltage can be set using supplied address bits.
- One advantage of this solution is that the use of the address bits in the command structure of the chip means that no additional complexity is necessary in the command decoder or in the control logic in order to transmit the nominal variable to the programming voltage pump.
- In addition, in the case in which security-related data is stored in the memory, the absence of the test pad removes a point of access for a potential hacker. The test commands can be permanently locked in the chip before it leaves the factory, so that no further manipulation is possible.
- Finally, the memory device requires less space on the chip, which means that the storage density of the chip can be increased for the same dimensions, or the chip can be made smaller for the same storage capacity.
- Accordingly, the test programming voltage which can be prescribed is, in particular, a voltage at which the memory cells, in the fault-free state, are just short of being reprogrammable.
- In accordance with an added feature of the invention, the memory cells preferably form an EEPROM array. However, other memory types in which a programming voltage is required in order to change the memory content and needs to be varied for test purposes are also possible.
- In accordance with an additional feature of the invention, the prescribable test programming voltage can be set in the test mode preferably using a programming command.
- In accordance with another feature of the invention, the switching device is a multiplexer.
- In accordance with a further feature of the invention, the programming voltage pump is regulated, so that a nominal variable for the test programming voltage can be prescribed in the test mode using the address bits.
- Other features which are considered as characteristic for the invention are set forth in the appended claims.
- Although the invention is illustrated and described herein as embodied in an electronic memory device, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
- The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
- FIG. 1 shows a basic circuit diagram of such an embodiment; and
- FIGS. 2a and 2 b show the structure of various commands to be applied to the circuit shown in FIG. 1.
- Referring now to the figures of the drawing in detail and first, particularly, to FIG. 1 thereof, there is shown an electronic memory device1 having inputs and
outputs 2, afirst circuit module 10 and asecond circuit module 20. The electronic memory device 1 also includes anaddress bus 30 connecting the twocircuit modules - The
first circuit module 10 comprises a command decoder and circuits for the drive logic. In addition, the inputs andoutputs 2 of the memory device 1 are connected to this module. - The
second circuit module 20 contains a memory array 21 with a plurality of individual memory cells, a programming voltage pump with aregulator 22 and also amultiplexer 23, to whose input 23 a theaddress bus 30 is connected. Themultiplexer 23 has two outputs 23 b, 23 c, one of which is connected to the memory array 21 and the other of which is connected to theprogramming voltage pump 22. Themultiplexer 23 fulfills the function of a changeover switch for theaddress bus 30 connected to its input 23 a between the memory array 21 and theprogramming voltage pump 22. The changeover procedure is controlled by means of a test mode signal supplied to acontrol input 23 d. - After such an electronic memory device1 has been manufactured, it needs to be tested for fault-free operability. In particular, it is necessary to ensure that the memory cells are reprogrammed only when a prescribed programming voltage is reached, and not beforehand at a much lower voltage. This is because this would present the risk of unintentionally changing the contents of the memory cells if, for example, the supply voltage rises on account of unforeseen circumstances. With an appropriate test, the programming voltage is lowered to a particular value in order to check whether the memory cells are just short of being able to be reprogrammed at this voltage. Since this test involves all the memory cells being examined at once, they do not need to be addressed.
- To carry out the test, therefore, the
multiplexer 23 is driven via itscontrol input 23 d by means of a test mode signal, so that theaddress bus 30 is now connected to the second output 23 c, which is connected to theprogramming voltage pump 22. Next, the programming voltage is lowered to the predetermined value via theaddress bus 30, and the address bits then enter the control loop of theprogramming voltage pump 22 directly and prescribe the new nominal variable for the lowered programming voltage. Finally, themultiplexer 23 is switched back again, and the memory cells can be examined to determine whether their contents have changed. - Setting the programming voltage can easily be implemented in the command structure of the chip.
- In the case of an inherently known structure (shown in FIG. 2a) of the read and programming commands with command, address and data parts, the programming command in the test mode can have the form shown in FIG. 2b. In this case,
bits 8 to 15 of the address part are used to set the test programming voltage, for example, while bits 0 to 7 of the command part can be used for further test mode settings or can be assigned the value “don't care”.
Claims (7)
1. An electronic memory device comprising:
electrically programmable memory cells;
an address bus for addressing said memory cells;
a controllable programming voltage pump for producing a programming voltage for said memory cells; and
a switching device configured for actuation in a test mode by a test mode signal and for connecting said address bus to said programming voltage pump in the test mode such that the programming voltage can be set to a predetermined test programming voltage using address bits supplied on said address bus.
2. The electronic memory device according to , wherein the predetermined test programming voltage is a voltage at which said memory cells, in a fault-free state, are just short of being re-programmable.
claim 1
3. The electronic memory device according to , comprising an EEPROM array formed by said memory cells.
claim 1
4. The electronic memory device according to , wherein the predetermined test programming voltage can be set in the test mode using a programming command.
claim 1
5. The electronic memory device according to , wherein said switching device is a multiplexer.
claim 1
6. The electronic memory device according to , wherein said programming voltage pump is a regulated voltage pump, and a nominal variable for the predetermined test programming voltage can be prescribed in the test mode using the address bits.
claim 1
7. The electronic memory device according to , wherein the address bits supplied in the test mode are stored in the memory device as a component part of one or more test programming commands and can be executed as required.
claim 1
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/DE1998/001738 WO1999067791A1 (en) | 1998-06-24 | 1998-06-24 | Electronic test memory device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE1998/001738 Continuation WO1999067791A1 (en) | 1998-06-24 | 1998-06-24 | Electronic test memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010002887A1 true US20010002887A1 (en) | 2001-06-07 |
US6366510B2 US6366510B2 (en) | 2002-04-02 |
Family
ID=6918657
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/748,473 Expired - Fee Related US6366510B2 (en) | 1998-06-24 | 2000-12-26 | Electronic memory device |
Country Status (12)
Country | Link |
---|---|
US (1) | US6366510B2 (en) |
EP (1) | EP1088311B1 (en) |
JP (1) | JP2002532813A (en) |
KR (1) | KR20010053128A (en) |
CN (1) | CN1127090C (en) |
AT (1) | ATE218004T1 (en) |
BR (1) | BR9815918A (en) |
DE (1) | DE59804216D1 (en) |
MX (1) | MXPA00012846A (en) |
RU (1) | RU2216796C2 (en) |
UA (1) | UA52828C2 (en) |
WO (1) | WO1999067791A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050036947A1 (en) * | 2003-08-12 | 2005-02-17 | General Electric Company | Target-specific activatable polymeric imaging agents |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7073094B1 (en) * | 2002-05-09 | 2006-07-04 | Winbond Electronics Corporation | Method and systems for programming and testing an embedded system |
JP2004110871A (en) * | 2002-09-13 | 2004-04-08 | Fujitsu Ltd | Nonvolatile semiconductor storage device |
JP2005071556A (en) * | 2003-08-28 | 2005-03-17 | Renesas Technology Corp | Semiconductor storage device and semiconductor integrated circuit device |
US10261876B2 (en) | 2016-11-08 | 2019-04-16 | Micron Technology, Inc. | Memory management |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5177745A (en) * | 1990-09-26 | 1993-01-05 | Intel Corporation | Memory device with a test mode |
US5291446A (en) | 1992-10-22 | 1994-03-01 | Advanced Micro Devices, Inc. | VPP power supply having a regulator circuit for controlling a regulated positive potential |
JP3331481B2 (en) * | 1993-07-14 | 2002-10-07 | 日本テキサス・インスツルメンツ株式会社 | Test circuit for semiconductor device |
US5606532A (en) * | 1995-03-17 | 1997-02-25 | Atmel Corporation | EEPROM array with flash-like core |
US5615159A (en) * | 1995-11-28 | 1997-03-25 | Micron Quantum Devices, Inc. | Memory system with non-volatile data storage unit and method of initializing same |
US5650734A (en) * | 1995-12-11 | 1997-07-22 | Altera Corporation | Programming programmable transistor devices using state machines |
KR0185611B1 (en) * | 1995-12-11 | 1999-04-15 | 김광호 | High voltage level optimization circuit of eeprom and its method |
US6154851A (en) * | 1997-08-05 | 2000-11-28 | Micron Technology, Inc. | Memory repair |
-
1998
- 1998-06-24 JP JP2000556377A patent/JP2002532813A/en active Pending
- 1998-06-24 BR BR9815918-6A patent/BR9815918A/en not_active IP Right Cessation
- 1998-06-24 KR KR1020007014666A patent/KR20010053128A/en not_active Application Discontinuation
- 1998-06-24 DE DE59804216T patent/DE59804216D1/en not_active Expired - Fee Related
- 1998-06-24 UA UA2000127462A patent/UA52828C2/en unknown
- 1998-06-24 RU RU2001102054/09A patent/RU2216796C2/en not_active IP Right Cessation
- 1998-06-24 EP EP98937408A patent/EP1088311B1/en not_active Expired - Lifetime
- 1998-06-24 CN CN98814133A patent/CN1127090C/en not_active Expired - Fee Related
- 1998-06-24 WO PCT/DE1998/001738 patent/WO1999067791A1/en not_active Application Discontinuation
- 1998-06-24 AT AT98937408T patent/ATE218004T1/en not_active IP Right Cessation
- 1998-06-24 MX MXPA00012846A patent/MXPA00012846A/en not_active Application Discontinuation
-
2000
- 2000-12-26 US US09/748,473 patent/US6366510B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050036947A1 (en) * | 2003-08-12 | 2005-02-17 | General Electric Company | Target-specific activatable polymeric imaging agents |
Also Published As
Publication number | Publication date |
---|---|
MXPA00012846A (en) | 2002-06-04 |
DE59804216D1 (en) | 2002-06-27 |
WO1999067791A1 (en) | 1999-12-29 |
US6366510B2 (en) | 2002-04-02 |
EP1088311A1 (en) | 2001-04-04 |
KR20010053128A (en) | 2001-06-25 |
EP1088311B1 (en) | 2002-05-22 |
BR9815918A (en) | 2001-02-20 |
CN1310847A (en) | 2001-08-29 |
ATE218004T1 (en) | 2002-06-15 |
UA52828C2 (en) | 2003-01-15 |
CN1127090C (en) | 2003-11-05 |
JP2002532813A (en) | 2002-10-02 |
RU2216796C2 (en) | 2003-11-20 |
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Legal Events
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AS | Assignment |
Owner name: SIEMENS AKTIENGESELLSCHAFT, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FIBRANZ, HEIKO;REEL/FRAME:012370/0622 Effective date: 20010118 |
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FPAY | Fee payment |
Year of fee payment: 4 |
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REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
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FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20100402 |