BR9813590A - Divisor de frequência, e, processo para controlar o mesmo. - Google Patents

Divisor de frequência, e, processo para controlar o mesmo.

Info

Publication number
BR9813590A
BR9813590A BR9813590-2A BR9813590A BR9813590A BR 9813590 A BR9813590 A BR 9813590A BR 9813590 A BR9813590 A BR 9813590A BR 9813590 A BR9813590 A BR 9813590A
Authority
BR
Brazil
Prior art keywords
frequency divider
state
frequency
control signals
reference clock
Prior art date
Application number
BR9813590-2A
Other languages
English (en)
Inventor
Hans Lennart Hagberg
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of BR9813590A publication Critical patent/BR9813590A/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H03K23/667—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Waveguide Switches, Polarizers, And Phase Shifters (AREA)
  • Amplifiers (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
  • Inorganic Insulating Materials (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
  • Optical Communication System (AREA)

Abstract

"DIVISOR DE FREQUêNCIA, E, PROCESSO PARA CONTROLAR O MESMO" Um divisor de frequência de multi-divisão, inclui uma cadeia de unidades de divisor de frequência conectadas serialmente, cada uma respondendo a um primeiro estado dos sinais de controle recebidos, usando o sinal de relógio de referência para gerar um sinal de saída possuindo uma frequência que é a frequência do relógio de referência dividida por um primeiro divisor, e cada uma respondendo a um segundo estado dos sinais de controle usando o sinal de relógio de referência para gerar um sinal de saída possuindo uma frequência que é a frequência de relógio de referência dividida por um segundo divisor. O sinal de saída pode ser fornecido a uma unidade de divisor de frequência sucessora na cadeia. A divisão pelo primeiro e segundo divisores faz com que o divisor de frequência tenha uma transição respectivamente através da primeira e segunda sequências de estado predeterminadas. Cada divisor de frequência responde adicionalmente a um terceiro estado dos sinais de controle, inicializando o divisor de frequência para um estado inicial que é comum a ambas primeiro e segunda sequências de estado predeterminadas, por meio do qual o divisor de frequência no estado inicial é imediatamente responsivo à aplicação subsequente do primeiro estado dos sinais de controle, e é imediatamente responsivo à aplicação subsequente do segundo estado dos sinais de controle. A recepção de um sinal de controle de habilitação para "absorver" possuindo um valor predeterminado desabilita a divisão pelo segundo divisor. Cada divisor de frequência gera adicionalmente um sinal de controle de saída possuindo o valor predeterminado, todas as vezes que o divisor de frequência está no estado inicial.
BR9813590-2A 1997-12-15 1998-12-08 Divisor de frequência, e, processo para controlar o mesmo. BR9813590A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/990,772 US5948046A (en) 1997-12-15 1997-12-15 Multi-divide frequency division
PCT/SE1998/002247 WO1999031805A1 (en) 1997-12-15 1998-12-08 Multi-divide frequency division

Publications (1)

Publication Number Publication Date
BR9813590A true BR9813590A (pt) 2000-10-10

Family

ID=25536515

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9813590-2A BR9813590A (pt) 1997-12-15 1998-12-08 Divisor de frequência, e, processo para controlar o mesmo.

Country Status (14)

Country Link
US (1) US5948046A (pt)
EP (1) EP1040581B1 (pt)
JP (1) JP4230665B2 (pt)
KR (1) KR100547535B1 (pt)
CN (1) CN1214532C (pt)
AT (1) ATE272268T1 (pt)
AU (1) AU751905B2 (pt)
BR (1) BR9813590A (pt)
DE (1) DE69825317D1 (pt)
EE (1) EE200000343A (pt)
HK (1) HK1034613A1 (pt)
IL (1) IL136619A (pt)
MY (1) MY120465A (pt)
WO (1) WO1999031805A1 (pt)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6157693A (en) * 1998-09-30 2000-12-05 Conexant Systems, Inc. Low voltage dual-modulus prescaler circuit using merged pseudo-differential logic
US6380773B1 (en) * 2000-12-01 2002-04-30 National Science Council Prescalar using fraction division theory
JP4386725B2 (ja) * 2001-08-29 2009-12-16 エヌエックスピー ビー ヴィ 低減されたジッタを備える改良された分周器及びそれに基づく送信器
US6753703B2 (en) * 2002-04-02 2004-06-22 Northrop Grumman Corporation Resetable cascadable divide-by-two circuit
DE10251703B4 (de) * 2002-11-06 2005-08-04 Infineon Technologies Ag Schaltungsanordnung zur Frequenzteilung und Phasenregelschleife mit der Schaltungsanordnung
US6894551B2 (en) * 2003-09-05 2005-05-17 Micron Technology, Inc. Multiphase clock generators
TWI222786B (en) * 2003-09-17 2004-10-21 Mediatek Inc Multi-modulus programmable frequency divider
US7027780B2 (en) * 2003-09-30 2006-04-11 Broadcom Corporation Technique for improving modulation performance of translational loop RF transmitters
CN1294701C (zh) * 2003-10-24 2007-01-10 立积电子股份有限公司 高频多样选择性预分频器
CN100371885C (zh) * 2003-11-17 2008-02-27 威盛电子股份有限公司 比率乘法的方法及比率乘法器
US7119587B2 (en) * 2004-05-20 2006-10-10 International Business Machines Corporation High frequency divider state correction circuit
US6961403B1 (en) 2004-05-28 2005-11-01 International Business Machines Corporation Programmable frequency divider with symmetrical output
JP3821441B2 (ja) * 2004-08-16 2006-09-13 松下電器産業株式会社 プリスケーラ回路
US7225092B2 (en) * 2004-10-21 2007-05-29 International Business Machines Corporation Method and apparatus for measuring and adjusting the duty cycle of a high speed clock
US7268597B2 (en) * 2005-02-16 2007-09-11 Avago Technologies General Ip (Singapore) Pte. Ltd. Self-initializing frequency divider
DE102005013328B3 (de) * 2005-03-22 2006-09-28 Infineon Technologies Ag Asynchroner Teiler mit einstellbarem Teilungsverhältnis
WO2007004465A1 (ja) * 2005-07-04 2007-01-11 Matsushita Electric Industrial Co., Ltd. 半導体装置およびそれを用いた無線回路装置
US7379522B2 (en) * 2006-01-11 2008-05-27 Qualcomm Incorporated Configurable multi-modulus frequency divider for multi-mode mobile communication devices
US7564276B2 (en) * 2006-06-28 2009-07-21 Qualcomm Incorporated Low-power modulus divider stage
JP5097573B2 (ja) * 2008-02-25 2012-12-12 ルネサスエレクトロニクス株式会社 分周回路
WO2010004508A1 (en) 2008-07-08 2010-01-14 Nxp B.V. Signal processing arrangement
CN102468842A (zh) * 2010-11-16 2012-05-23 北京中电华大电子设计有限责任公司 一种同步计数器电路及其实现方法
WO2012103090A1 (en) * 2011-01-28 2012-08-02 Coherent Logix, Incorporated Frequency divider with synchronous range extension across octave boundaries
US8744037B2 (en) * 2012-06-11 2014-06-03 Intel Mobil Communications GmbH Divider, method for providing an output signal and edge tracker
CN103138747B (zh) * 2013-01-27 2016-08-03 长春理工大学 基于单片机的可预置分频数的任意整数分频器
US9490826B1 (en) * 2015-08-19 2016-11-08 Qualcomm Incorporated Methods and apparatus for synchronizing frequency dividers using a pulse swallowing technique

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4494243A (en) * 1981-11-26 1985-01-15 Itt Industries, Inc. Frequency divider presettable to fractional divisors
US4669099A (en) * 1985-10-15 1987-05-26 The Singer Company Digital frequency multiplier
JP2572283B2 (ja) * 1989-10-23 1997-01-16 日本無線株式会社 可変分周回路
US4965531A (en) * 1989-11-22 1990-10-23 Carleton University Frequency synthesizers having dividing ratio controlled by sigma-delta modulator
US5055802A (en) * 1990-04-30 1991-10-08 Motorola, Inc. Multiaccumulator sigma-delta fractional-n synthesis
JP2853894B2 (ja) * 1990-08-24 1999-02-03 三菱電機株式会社 分周回路及びパルス信号作成回路
US5195111A (en) * 1990-09-07 1993-03-16 Nihon Musen Kabushiki Kaisha Programmable frequency dividing apparatus
FR2677515A1 (fr) * 1991-06-07 1992-12-11 Philips Composants Circuit diviseur de frequence.
FR2719728A1 (fr) * 1994-05-04 1995-11-10 Philips Composants Diviseur de fréquence, synthétiseur de fréquence comportant un tel diviseur et radiotéléphone comportant un tel synthétiseur.

Also Published As

Publication number Publication date
KR100547535B1 (ko) 2006-01-31
DE69825317D1 (de) 2004-09-02
CN1282465A (zh) 2001-01-31
EE200000343A (et) 2001-08-15
AU751905B2 (en) 2002-08-29
MY120465A (en) 2005-10-31
WO1999031805A1 (en) 1999-06-24
JP2002509376A (ja) 2002-03-26
CN1214532C (zh) 2005-08-10
EP1040581B1 (en) 2004-07-28
IL136619A0 (en) 2001-06-14
EP1040581A1 (en) 2000-10-04
US5948046A (en) 1999-09-07
ATE272268T1 (de) 2004-08-15
JP4230665B2 (ja) 2009-02-25
HK1034613A1 (en) 2001-10-26
AU1896199A (en) 1999-07-05
IL136619A (en) 2005-09-25
KR20010024713A (ko) 2001-03-26

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Legal Events

Date Code Title Description
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09B Patent application refused [chapter 9.2 patent gazette]

Free format text: INDEFIRO O PEDIDO DE ACORDO COM O ART. 8O COMBINADO COM ART.13 DA LPI.

B09B Patent application refused [chapter 9.2 patent gazette]

Free format text: MANTIDO O INDEFERIMENTO UMA VEZ QUE NAO FOI APRESENTADO RECURSO DENTRO DO PRAZO LEGAL.