JPS6433792A - Refresh interval timer - Google Patents

Refresh interval timer

Info

Publication number
JPS6433792A
JPS6433792A JP62191238A JP19123887A JPS6433792A JP S6433792 A JPS6433792 A JP S6433792A JP 62191238 A JP62191238 A JP 62191238A JP 19123887 A JP19123887 A JP 19123887A JP S6433792 A JPS6433792 A JP S6433792A
Authority
JP
Japan
Prior art keywords
circuit
cpu
refresh
register
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62191238A
Other languages
Japanese (ja)
Inventor
Tomoya Aoki
Koichi Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Niigata Fuji Xerox Manufacturing Co Ltd
Original Assignee
NEC Corp
Niigata Fuji Xerox Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Niigata Fuji Xerox Manufacturing Co Ltd filed Critical NEC Corp
Priority to JP62191238A priority Critical patent/JPS6433792A/en
Publication of JPS6433792A publication Critical patent/JPS6433792A/en
Pending legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To execute the management of one CPU to the management of other CPU within a specification time by providing an I/O decoder, a register, a synchronizing circuit, an AND circuit, a counter, etc., to the CPU and executing refresh in a short interval. CONSTITUTION:A writing to a refresh timer register 7 is executed by a signal obtained by decoding the address bus 4 of the CPU 2 and a write signal 5 by the I/O decoder 6. The timer start and stop data 16 of the output signal of the register 7 is supplied to the synchronizing circuit 9 consisting of the FF10, synchronized with a basic clock 1 inputted to the CPU 2 and outputted. The AND circuit 11 inputs the output of the circuit 9 and the basic clock 1, inputs a clock to the counter part 12 when data 15 is '1' and inhibits an input when it is '0'. The output of the circuit 9 indicates the stop during the operation of the counter part 12 and outputs a signal 15. Then, the counter part 12 outputs a refresh request pulse 14 at the time interval based on refresh interval time preset data 8.
JP62191238A 1987-07-30 1987-07-30 Refresh interval timer Pending JPS6433792A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62191238A JPS6433792A (en) 1987-07-30 1987-07-30 Refresh interval timer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62191238A JPS6433792A (en) 1987-07-30 1987-07-30 Refresh interval timer

Publications (1)

Publication Number Publication Date
JPS6433792A true JPS6433792A (en) 1989-02-03

Family

ID=16271198

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62191238A Pending JPS6433792A (en) 1987-07-30 1987-07-30 Refresh interval timer

Country Status (1)

Country Link
JP (1) JPS6433792A (en)

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