JPS5787263A - Time control device for transmission control procedure - Google Patents
Time control device for transmission control procedureInfo
- Publication number
- JPS5787263A JPS5787263A JP55162295A JP16229580A JPS5787263A JP S5787263 A JPS5787263 A JP S5787263A JP 55162295 A JP55162295 A JP 55162295A JP 16229580 A JP16229580 A JP 16229580A JP S5787263 A JPS5787263 A JP S5787263A
- Authority
- JP
- Japan
- Prior art keywords
- register
- output
- control device
- count
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer And Data Communications (AREA)
- Communication Control (AREA)
Abstract
PURPOSE:To simplify software, by starting a register by the count-up output of a counter to control the state of another register. CONSTITUTION:The output of a processing part 1 of a microcomputer is latched in a register 6 through a register 2. This register 6 decodes 3-bit data of the register 2 to 0-7 and output it. A counter 7 is controlled by an output line 1 of the register 6 to start counting. The count-up output of the counter 7 is fed back to the processing part 1 of the computer, and a register 3 is started by the count-up output, and the state of the register 2 is controlled by the output of the register 3.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55162295A JPS5787263A (en) | 1980-11-18 | 1980-11-18 | Time control device for transmission control procedure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55162295A JPS5787263A (en) | 1980-11-18 | 1980-11-18 | Time control device for transmission control procedure |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5787263A true JPS5787263A (en) | 1982-05-31 |
JPS6142985B2 JPS6142985B2 (en) | 1986-09-25 |
Family
ID=15751771
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55162295A Granted JPS5787263A (en) | 1980-11-18 | 1980-11-18 | Time control device for transmission control procedure |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5787263A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0426148Y2 (en) * | 1986-10-31 | 1992-06-23 |
-
1980
- 1980-11-18 JP JP55162295A patent/JPS5787263A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6142985B2 (en) | 1986-09-25 |
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