JPS57191754A - Data processing device - Google Patents

Data processing device

Info

Publication number
JPS57191754A
JPS57191754A JP56076107A JP7610781A JPS57191754A JP S57191754 A JPS57191754 A JP S57191754A JP 56076107 A JP56076107 A JP 56076107A JP 7610781 A JP7610781 A JP 7610781A JP S57191754 A JPS57191754 A JP S57191754A
Authority
JP
Japan
Prior art keywords
check
turned
registers
parts
executed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56076107A
Other languages
Japanese (ja)
Inventor
Hideho Masuzawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56076107A priority Critical patent/JPS57191754A/en
Publication of JPS57191754A publication Critical patent/JPS57191754A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

PURPOSE:To shorten the processing time, by checking whether instructions can be executed or not in parallel. CONSTITUTION:Control memories 33-1-33-4 are incorporated in check parts 21-2-21-4 connected in parallel. When a request flag 26-1 is turned on, a preceding stage request flag controlling part 25 determines one of check parts 21-1- 21-4. One of request acceptance flag registers 22-1-22-4 which corresponds to the determined check part out of check parts 22-1-22-4 is turned on to fetch data into one of input registers 32-1-32-4. When registers 22-1-22-4 are turned on, check parts 21-1-21-4 check whether instructions can be executed or not.
JP56076107A 1981-05-20 1981-05-20 Data processing device Pending JPS57191754A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56076107A JPS57191754A (en) 1981-05-20 1981-05-20 Data processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56076107A JPS57191754A (en) 1981-05-20 1981-05-20 Data processing device

Publications (1)

Publication Number Publication Date
JPS57191754A true JPS57191754A (en) 1982-11-25

Family

ID=13595665

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56076107A Pending JPS57191754A (en) 1981-05-20 1981-05-20 Data processing device

Country Status (1)

Country Link
JP (1) JPS57191754A (en)

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