JPS56166556A - Controlling circuit - Google Patents
Controlling circuitInfo
- Publication number
- JPS56166556A JPS56166556A JP6939780A JP6939780A JPS56166556A JP S56166556 A JPS56166556 A JP S56166556A JP 6939780 A JP6939780 A JP 6939780A JP 6939780 A JP6939780 A JP 6939780A JP S56166556 A JPS56166556 A JP S56166556A
- Authority
- JP
- Japan
- Prior art keywords
- program counter
- instruction
- return
- controlling circuit
- constant address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
- G06F9/4482—Procedural
- G06F9/4484—Executing subprograms
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
Abstract
PURPOSE:To prevent an infinite loop from being formed, by loading a constant address to a program counter if a return instruction which does not make a pair with a call instruction is executed in the controlling circuit of the microcomputer system. CONSTITUTION:A constant address is written into a stack 3 from which data transfer to a program counter 2 is completed by a return instruction; and if the return instruction which does not make a pair with a call instruction is executed to generate an infinite loop, the constant address written in the stack 3 is loaded to the program counter 2 to return the control to a normal loop through the routine of error processing.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55069397A JPS6052454B2 (en) | 1980-05-23 | 1980-05-23 | control circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55069397A JPS6052454B2 (en) | 1980-05-23 | 1980-05-23 | control circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56166556A true JPS56166556A (en) | 1981-12-21 |
JPS6052454B2 JPS6052454B2 (en) | 1985-11-19 |
Family
ID=13401421
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55069397A Expired JPS6052454B2 (en) | 1980-05-23 | 1980-05-23 | control circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6052454B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8701857B2 (en) | 2000-02-11 | 2014-04-22 | Cummins-Allison Corp. | System and method for processing currency bills and tickets |
-
1980
- 1980-05-23 JP JP55069397A patent/JPS6052454B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS6052454B2 (en) | 1985-11-19 |
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