JPS6459554A - Data processor - Google Patents
Data processorInfo
- Publication number
- JPS6459554A JPS6459554A JP21731087A JP21731087A JPS6459554A JP S6459554 A JPS6459554 A JP S6459554A JP 21731087 A JP21731087 A JP 21731087A JP 21731087 A JP21731087 A JP 21731087A JP S6459554 A JPS6459554 A JP S6459554A
- Authority
- JP
- Japan
- Prior art keywords
- input
- processing
- output device
- function
- error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To shorten the processing time of an input/output instruction in a basic processor, by providing a function to fetch channel information and a function to check the validity of fetch information on the basic processor, an a function to judge the acceptable state of a processing and a function to transfer data on an input/output device. CONSTITUTION:The basic processor 6 fetches the channel information before issuing the indication of the input/output instruction to the input/output device 7, and saves the channel information in a specific area if no error exists, and after that, supplies the indication of the input/output instruction to the input/ output device 7. The input/output device 7, when judging a state as the acceptable state of the processing, checks a checked result with respect to the validity of the fetch information by an error flag, and when it is judged that the error exists, performs an error processing by setting error processing state information. In such a way, it is possible to shorten the processing time of the input/ output instruction in the basic processor even when the input/output device operated at slow processing speed is used.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21731087A JPS6459554A (en) | 1987-08-31 | 1987-08-31 | Data processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21731087A JPS6459554A (en) | 1987-08-31 | 1987-08-31 | Data processor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6459554A true JPS6459554A (en) | 1989-03-07 |
Family
ID=16702150
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21731087A Pending JPS6459554A (en) | 1987-08-31 | 1987-08-31 | Data processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6459554A (en) |
-
1987
- 1987-08-31 JP JP21731087A patent/JPS6459554A/en active Pending
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