JPS5525135A - Clock control system - Google Patents

Clock control system

Info

Publication number
JPS5525135A
JPS5525135A JP9766178A JP9766178A JPS5525135A JP S5525135 A JPS5525135 A JP S5525135A JP 9766178 A JP9766178 A JP 9766178A JP 9766178 A JP9766178 A JP 9766178A JP S5525135 A JPS5525135 A JP S5525135A
Authority
JP
Japan
Prior art keywords
control
clocks
counter
advance
free
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9766178A
Other languages
Japanese (ja)
Other versions
JPS5947334B2 (en
Inventor
Masatake Iwato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53097661A priority Critical patent/JPS5947334B2/en
Publication of JPS5525135A publication Critical patent/JPS5525135A/en
Publication of JPS5947334B2 publication Critical patent/JPS5947334B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To simplify the clock control of a digital computer by controlling the start and stop of the generation of control clocks and the continuation of several periods by using the each-digit output of control and free clock counters to advance control clocks and free clocks.
CONSTITUTION: Through the control with a fundamental clock period taken as 1T, the (n)-number control clocks of periods 1T, 2T... 2n+T are generated and supplied as free clock of periods 1T, 2T...2n-1T which do not control the generation. At this time, each-digit outputs of n-bit binary counter controlled respectively and n-bit binary counter whose advance is not controlled are used to advance those control clocks and free clocks. When the controller restarts the generation of control clocks after a temporarily break, the content of the control counter is compared with that of the free counter and after the advance of the control counter is restarted, the advance start timing of the control counter is determined so as to equalize the both counter in content.
COPYRIGHT: (C)1980,JPO&Japio
JP53097661A 1978-08-10 1978-08-10 Clock control method Expired JPS5947334B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53097661A JPS5947334B2 (en) 1978-08-10 1978-08-10 Clock control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53097661A JPS5947334B2 (en) 1978-08-10 1978-08-10 Clock control method

Publications (2)

Publication Number Publication Date
JPS5525135A true JPS5525135A (en) 1980-02-22
JPS5947334B2 JPS5947334B2 (en) 1984-11-19

Family

ID=14198238

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53097661A Expired JPS5947334B2 (en) 1978-08-10 1978-08-10 Clock control method

Country Status (1)

Country Link
JP (1) JPS5947334B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0253123A (en) * 1988-08-18 1990-02-22 Fujitsu Ltd Clock cycle setting device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0253123A (en) * 1988-08-18 1990-02-22 Fujitsu Ltd Clock cycle setting device

Also Published As

Publication number Publication date
JPS5947334B2 (en) 1984-11-19

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