BR9203918A - Microplaqueta de memoria exclusiva que permite a concatenacao de ilhas e sistema que a engloba - Google Patents

Microplaqueta de memoria exclusiva que permite a concatenacao de ilhas e sistema que a engloba

Info

Publication number
BR9203918A
BR9203918A BR929203918A BR9203918A BR9203918A BR 9203918 A BR9203918 A BR 9203918A BR 929203918 A BR929203918 A BR 929203918A BR 9203918 A BR9203918 A BR 9203918A BR 9203918 A BR9203918 A BR 9203918A
Authority
BR
Brazil
Prior art keywords
islands
concatenation
english
allows
memory chip
Prior art date
Application number
BR929203918A
Other languages
English (en)
Inventor
Warren W Grunbok
Billy J Knowles
William R Milani
Douglas R Moran
Dale E Pontius
Donald W Price
Robert Tamlyn
Yee-Mine Ting
De Tran
Henry Yeh
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BR9203918A publication Critical patent/BR9203918A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1657—Access to multiple memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Image Input (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Hardware Redundancy (AREA)
BR929203918A 1991-10-31 1992-10-08 Microplaqueta de memoria exclusiva que permite a concatenacao de ilhas e sistema que a engloba BR9203918A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/786,139 US5278800A (en) 1991-10-31 1991-10-31 Memory system and unique memory chip allowing island interlace

Publications (1)

Publication Number Publication Date
BR9203918A true BR9203918A (pt) 1993-05-04

Family

ID=25137699

Family Applications (1)

Application Number Title Priority Date Filing Date
BR929203918A BR9203918A (pt) 1991-10-31 1992-10-08 Microplaqueta de memoria exclusiva que permite a concatenacao de ilhas e sistema que a engloba

Country Status (5)

Country Link
US (1) US5278800A (pt)
EP (1) EP0540363A1 (pt)
JP (1) JPH05216749A (pt)
BR (1) BR9203918A (pt)
CA (1) CA2074879A1 (pt)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994003901A1 (en) 1992-08-10 1994-02-17 Monolithic System Technology, Inc. Fault-tolerant, high-speed bus system and bus interface for wafer-scale integration
US5655113A (en) * 1994-07-05 1997-08-05 Monolithic System Technology, Inc. Resynchronization circuit for a memory system and method of operating same
US5508968A (en) * 1994-08-12 1996-04-16 International Business Machines Corporation Dynamic random access memory persistent page implemented as processor register sets
DE69514502T2 (de) * 1995-05-05 2000-08-03 Stmicroelectronics S.R.L., Agrate Brianza Nichtflüchtige Speicheranordnung mit Sektoren, deren Grösse und Anzahl bestimmbar sind
EP0745995B1 (en) * 1995-05-05 2001-04-11 STMicroelectronics S.r.l. Nonvolatile, in particular flash-EEPROM, memory device

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3449724A (en) * 1966-09-12 1969-06-10 Ibm Control system for interleave memory
US3863232A (en) * 1973-12-26 1975-01-28 Ibm Associative array
DE2537787A1 (de) * 1975-08-25 1977-03-03 Computer Ges Konstanz Modularer arbeitsspeicher fuer eine datenverarbeitungsanlage und verfahren zum durchfuehren von speicherzugriffen an diesem speicher
US4117546A (en) * 1977-12-30 1978-09-26 International Business Machines Corporation Interlaced ccd memory
DE3141882A1 (de) * 1981-10-22 1983-05-05 Agfa-Gevaert Ag, 5090 Leverkusen Dynamische schreib- und lesespeichervorrichtung
JPS58142459A (ja) * 1982-02-19 1983-08-24 Hitachi Ltd 主記憶装置
JPS59148950A (ja) * 1983-02-14 1984-08-25 Fujitsu Ltd パイプライン処理におけるメモリ制御方式
JPS6386974A (ja) * 1986-09-30 1988-04-18 Nec Corp 電荷転送撮像素子とその駆動方法
US4845677A (en) * 1987-08-17 1989-07-04 International Business Machines Corporation Pipelined memory chip structure having improved cycle time
US4924375A (en) * 1987-10-23 1990-05-08 Chips And Technologies, Inc. Page interleaved memory access
US5150328A (en) * 1988-10-25 1992-09-22 Internation Business Machines Corporation Memory organization with arrays having an alternate data port facility
US5047921A (en) * 1989-01-31 1991-09-10 International Business Machines Corporation Asynchronous microprocessor random access memory arbitration controller
US4954987A (en) * 1989-07-17 1990-09-04 Advanced Micro Devices, Inc. Interleaved sensing system for FIFO and burst-mode memories
US5060145A (en) * 1989-09-06 1991-10-22 Unisys Corporation Memory access system for pipelined data paths to and from storage

Also Published As

Publication number Publication date
CA2074879A1 (en) 1993-05-01
JPH05216749A (ja) 1993-08-27
US5278800A (en) 1994-01-11
EP0540363A1 (en) 1993-05-05

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Legal Events

Date Code Title Description
EE Request for examination
FB36 Technical and formal requirements: requirement - article 36 of industrial property law
FA8 Dismissal: dismissal - article 36, par. 1 of industrial property law