BR8901841A - Sistema de graficos de computador e processo para opera-lo - Google Patents

Sistema de graficos de computador e processo para opera-lo

Info

Publication number
BR8901841A
BR8901841A BR898901841A BR8901841A BR8901841A BR 8901841 A BR8901841 A BR 8901841A BR 898901841 A BR898901841 A BR 898901841A BR 8901841 A BR8901841 A BR 8901841A BR 8901841 A BR8901841 A BR 8901841A
Authority
BR
Brazil
Prior art keywords
memory
display
large area
operate
computer graphics
Prior art date
Application number
BR898901841A
Other languages
English (en)
Inventor
Satish Gupta
Steven Philip Larky
Alan Wesley Peevers
Joe Christopher St Clair
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BR8901841A publication Critical patent/BR8901841A/pt

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/14—Display of multiple viewports
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Digital Computer Display Output (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Circuits Of Receivers In General (AREA)
  • Telephone Function (AREA)
  • Transceivers (AREA)
  • Processing Or Creating Images (AREA)
  • Image Generation (AREA)
BR898901841A 1988-04-20 1989-04-19 Sistema de graficos de computador e processo para opera-lo BR8901841A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/183,795 US5113180A (en) 1988-04-20 1988-04-20 Virtual display adapter

Publications (1)

Publication Number Publication Date
BR8901841A true BR8901841A (pt) 1989-11-28

Family

ID=22674321

Family Applications (1)

Application Number Title Priority Date Filing Date
BR898901841A BR8901841A (pt) 1988-04-20 1989-04-19 Sistema de graficos de computador e processo para opera-lo

Country Status (8)

Country Link
US (1) US5113180A (pt)
EP (1) EP0338416B1 (pt)
JP (1) JP2538029B2 (pt)
AT (1) ATE110873T1 (pt)
BR (1) BR8901841A (pt)
CA (1) CA1313415C (pt)
DE (1) DE68917771T2 (pt)
ES (1) ES2060684T3 (pt)

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US5519829A (en) * 1990-08-03 1996-05-21 3Dlabs Ltd. Data-array processing and memory systems
WO1992002922A1 (en) * 1990-08-03 1992-02-20 Du Pont Pixel Systems Limited Data-array processing and memory systems
WO1992002879A1 (en) * 1990-08-03 1992-02-20 Du Pont Pixel Systems Limited Virtual memory system
US5289574A (en) * 1990-09-17 1994-02-22 Hewlett-Packard Company Multiple virtual screens on an "X windows" terminal
GB9108389D0 (en) * 1991-04-19 1991-06-05 3 Space Software Ltd Treatment of video images
US5291188A (en) * 1991-06-17 1994-03-01 Sun Microsystems, Inc. Method and apparatus for allocating off-screen display memory
JPH05189549A (ja) * 1991-09-10 1993-07-30 Kubota Corp マルチプロセッサによる画像データ処理装置
US5675762A (en) * 1992-04-03 1997-10-07 International Business Machines Corporation System for locking down part of portion of memory and updating page directory with entry corresponding to part of portion of the memory locked down
US5396597A (en) * 1992-04-03 1995-03-07 International Business Machines Corporation System for transferring data between processors via dual buffers within system memory with first and second processors accessing system memory directly and indirectly
US5473348A (en) * 1992-06-09 1995-12-05 Kabushiki Kaisha Toshiba Apparatus and method of controlling paging unit of coprocessor built in display control system
JP2761335B2 (ja) * 1992-10-21 1998-06-04 三菱電機株式会社 画面表示装置
US5592670A (en) * 1992-11-02 1997-01-07 Microsoft Corporation Avoidance of deadlocks in a demand paged video adapter
US5739811A (en) * 1993-07-16 1998-04-14 Immersion Human Interface Corporation Method and apparatus for controlling human-computer interface systems providing force feedback
US5477242A (en) * 1994-01-03 1995-12-19 International Business Machines Corporation Display adapter for virtual VGA support in XGA native mode
US5748866A (en) * 1994-06-30 1998-05-05 International Business Machines Corporation Virtual display adapters using a digital signal processing to reformat different virtual displays into a common format and display
US6067098A (en) * 1994-11-16 2000-05-23 Interactive Silicon, Inc. Video/graphics controller which performs pointer-based display list video refresh operation
US5838334A (en) * 1994-11-16 1998-11-17 Dye; Thomas A. Memory and graphics controller which performs pointer-based display list video refresh operations
US6002411A (en) * 1994-11-16 1999-12-14 Interactive Silicon, Inc. Integrated video and memory controller with data processing and graphical processing capabilities
US6195710B1 (en) * 1995-06-12 2001-02-27 International Business Machines Corporation Operating system having shared personality neutral resources
US5946005A (en) * 1995-09-21 1999-08-31 Industrial Technology Research Institute Computer graphics memory architecture having a graphics processor and a buffer
US6111584A (en) * 1995-12-18 2000-08-29 3Dlabs Inc. Ltd. Rendering system with mini-patch retrieval from local texture storage
US6308248B1 (en) * 1996-12-31 2001-10-23 Compaq Computer Corporation Method and system for allocating memory space using mapping controller, page table and frame numbers
US6333750B1 (en) 1997-03-12 2001-12-25 Cybex Computer Products Corporation Multi-sourced video distribution hub
US6104414A (en) * 1997-03-12 2000-08-15 Cybex Computer Products Corporation Video distribution hub
US6600493B1 (en) * 1999-12-29 2003-07-29 Intel Corporation Allocating memory based on memory device organization
US6724390B1 (en) 1999-12-29 2004-04-20 Intel Corporation Allocating memory
US6943801B2 (en) * 2000-03-31 2005-09-13 Scott A. Rosenberg System and method for refreshing imaging devices or displays on a page-level basis
US7015919B1 (en) * 2002-01-08 2006-03-21 Apple Computer, Inc. Virtualization of graphics resources
US7768522B2 (en) 2002-01-08 2010-08-03 Apple Inc. Virtualization of graphics resources and thread blocking
US6809736B1 (en) 2002-01-08 2004-10-26 Apple Computer, Inc. Virtualization of graphics resources
US6809735B1 (en) * 2002-01-08 2004-10-26 Apple Computer, Inc. Virtualization of graphics resources
US7421694B2 (en) * 2003-02-18 2008-09-02 Microsoft Corporation Systems and methods for enhancing performance of a coprocessor
US7673304B2 (en) * 2003-02-18 2010-03-02 Microsoft Corporation Multithreaded kernel for graphics processing unit
US8643659B1 (en) 2003-12-31 2014-02-04 3Dlabs Inc., Ltd. Shader with global and instruction caches
US9007383B2 (en) 2012-12-05 2015-04-14 Vysoká {hacek over (s)}kola bá{hacek over (n)}ská—Technická Univerzita Ostrava Creating presentations by capturing content of a simulated second monitor

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US4096568A (en) * 1976-09-24 1978-06-20 Sperry Rand Corporation Virtual address translator
US4325120A (en) * 1978-12-21 1982-04-13 Intel Corporation Data processing system
US4249172A (en) * 1979-09-04 1981-02-03 Honeywell Information Systems Inc. Row address linking control system for video display terminal
US4484302A (en) * 1980-11-20 1984-11-20 International Business Machines Corporation Single screen display system with multiple virtual display having prioritized service programs and dedicated memory stacks
JPS58105339A (ja) * 1981-12-17 1983-06-23 Fujitsu Ltd 図形の表示印刷方式
EP0099989B1 (en) * 1982-06-28 1990-11-14 Kabushiki Kaisha Toshiba Image display control apparatus
US4598384A (en) * 1983-04-22 1986-07-01 International Business Machines Corp. Graphics display with improved window organization
JPS59214944A (ja) * 1983-05-20 1984-12-04 Hitachi Ltd 図形出力端末装置
JPS6074085A (ja) * 1983-09-30 1985-04-26 Fujitsu Ltd イメ−ジメモリ制御方法
US4651146A (en) * 1983-10-17 1987-03-17 International Business Machines Corporation Display of multiple data windows in a multi-tasking system
JPS60147785A (ja) * 1984-01-12 1985-08-03 株式会社アスキ− 論理領域間デ−タ移動制御装置
JPS60222889A (ja) * 1984-04-20 1985-11-07 株式会社リコー 表示制御装置
FR2566951B1 (fr) * 1984-06-29 1986-12-26 Texas Instruments France Procede et systeme pour l'affichage d'informations visuelles sur un ecran par balayage ligne par ligne et point par point de trames video
EP0482678B1 (en) * 1984-07-23 1998-01-14 Texas Instruments Incorporated Video system
US4688167A (en) * 1984-09-27 1987-08-18 Wang Laboratories, Inc. Screen manager for data processing system
JPS6228850A (ja) * 1985-07-31 1987-02-06 Toshiba Corp メモリアドレスマツピング機構
US4912658A (en) * 1986-04-18 1990-03-27 Advanced Micro Devices, Inc. Method and apparatus for addressing video RAMS and refreshing a video monitor with a variable resolution
JPS63115227A (ja) * 1986-10-31 1988-05-19 Nec Corp 画面表示アドレス変換装置
US4809142A (en) * 1987-09-09 1989-02-28 Seymour Auerbach Integrated lighting device
US4955024A (en) * 1987-09-14 1990-09-04 Visual Information Technologies, Inc. High speed image processing computer with error correction and logging

Also Published As

Publication number Publication date
ATE110873T1 (de) 1994-09-15
JP2538029B2 (ja) 1996-09-25
ES2060684T3 (es) 1994-12-01
CA1313415C (en) 1993-02-02
EP0338416A3 (en) 1991-12-11
JPH0212523A (ja) 1990-01-17
EP0338416A2 (en) 1989-10-25
DE68917771D1 (de) 1994-10-06
US5113180A (en) 1992-05-12
DE68917771T2 (de) 1995-03-30
EP0338416B1 (en) 1994-08-31

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Legal Events

Date Code Title Description
KF Request for proof of payment of annual fee
FD5 Application fees: dismissal - article 86 of industrial property law