BR8507078A - Estrutura de fiacao de circuito de terminacao - Google Patents

Estrutura de fiacao de circuito de terminacao

Info

Publication number
BR8507078A
BR8507078A BR8507078A BR8507078A BR8507078A BR 8507078 A BR8507078 A BR 8507078A BR 8507078 A BR8507078 A BR 8507078A BR 8507078 A BR8507078 A BR 8507078A BR 8507078 A BR8507078 A BR 8507078A
Authority
BR
Brazil
Prior art keywords
wire structure
termination circuit
circuit wire
termination
wire
Prior art date
Application number
BR8507078A
Other languages
English (en)
Portuguese (pt)
Inventor
Mikio Nishihara
Kiyoshi Kuwabara
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of BR8507078A publication Critical patent/BR8507078A/pt

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09627—Special connections between adjacent vias, not for grounding vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10522—Adjacent components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
  • Multi-Conductor Connections (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
BR8507078A 1984-11-29 1985-11-28 Estrutura de fiacao de circuito de terminacao BR8507078A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59253562A JPS61131498A (ja) 1984-11-29 1984-11-29 終端回路配線構造
PCT/JP1985/000661 WO1986003365A1 (fr) 1984-11-29 1985-11-28 Structure de cablage d'un circuit terminal

Publications (1)

Publication Number Publication Date
BR8507078A true BR8507078A (pt) 1987-03-31

Family

ID=17253090

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8507078A BR8507078A (pt) 1984-11-29 1985-11-28 Estrutura de fiacao de circuito de terminacao

Country Status (8)

Country Link
US (1) US4785141A (enExample)
EP (1) EP0204004B1 (enExample)
JP (1) JPS61131498A (enExample)
KR (1) KR900005305B1 (enExample)
AU (1) AU580828B2 (enExample)
BR (1) BR8507078A (enExample)
DE (1) DE3585445D1 (enExample)
WO (1) WO1986003365A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63195772U (enExample) * 1987-06-05 1988-12-16
US5001605A (en) * 1988-11-30 1991-03-19 Hughes Aircraft Company Multilayer printed wiring board with single layer vias
DE8903913U1 (de) * 1989-03-30 1989-05-18 Siemens AG, 1000 Berlin und 8000 München Leiterplattenförmiges Busverdrahtungsfeld
JPH04109838U (ja) * 1991-03-08 1992-09-24 オークマ株式会社 パレツト交換装置におけるパレツト把持装置
US5117331A (en) * 1991-05-16 1992-05-26 Compaq Computer Corporation Bus control signal routing and termination
US5175515A (en) * 1991-06-21 1992-12-29 Compaq Computer Corporation Signal routing technique for electronic systems
US5414219A (en) * 1994-04-22 1995-05-09 At&T Corp. Printed circuit board circuit control device
US7269028B2 (en) * 1997-10-16 2007-09-11 Celestica, Inc. Trace-pad interface for improved signal quality
US10716210B2 (en) * 2015-09-15 2020-07-14 Hewlett Packard Enterprise Development Lp Printed circuit board including through-hole vias

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3243498A (en) * 1964-12-24 1966-03-29 Ibm Method for making circuit connections to internal layers of a multilayer circuit card and circuit card produced thereby
FR2241946B1 (enExample) * 1973-08-24 1976-11-19 Honeywell Bull Soc Ind
JPS53129863A (en) * 1977-04-19 1978-11-13 Fujitsu Ltd Multilayer printed board
FR2404990A1 (fr) * 1977-10-03 1979-04-27 Cii Honeywell Bull Substrat d'interconnexion de composants electroniques a circuits integres, muni d'un dispositif de reparation
US4245273A (en) * 1979-06-29 1981-01-13 International Business Machines Corporation Package for mounting and interconnecting a plurality of large scale integrated semiconductor devices
FR2555011B1 (fr) * 1983-11-15 1986-01-24 Thomson Csf Carte imprimee a empreintes
JPS60136294A (ja) * 1983-12-23 1985-07-19 株式会社日立製作所 セラミック多層配線回路板
US4562513A (en) * 1984-05-21 1985-12-31 International Business Machines Corporation Process for forming a high density metallurgy system on a substrate and structure thereof
US4546413A (en) * 1984-06-29 1985-10-08 International Business Machines Corporation Engineering change facility on both major surfaces of chip module
JPS61131497A (ja) * 1984-11-29 1986-06-19 富士通株式会社 多層プリント基板

Also Published As

Publication number Publication date
JPH0227836B2 (enExample) 1990-06-20
KR880700614A (ko) 1988-03-15
WO1986003365A1 (fr) 1986-06-05
EP0204004B1 (en) 1992-02-26
KR900005305B1 (ko) 1990-07-27
AU5193886A (en) 1986-06-18
DE3585445D1 (de) 1992-04-02
US4785141A (en) 1988-11-15
JPS61131498A (ja) 1986-06-19
AU580828B2 (en) 1989-02-02
EP0204004A4 (en) 1987-07-30
EP0204004A1 (en) 1986-12-10

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Legal Events

Date Code Title Description
MM Lapse due to non-payment of fees (art. 50)