BR8306653A - Processo para fazer transistores complementares - Google Patents
Processo para fazer transistores complementaresInfo
- Publication number
- BR8306653A BR8306653A BR8306653A BR8306653A BR8306653A BR 8306653 A BR8306653 A BR 8306653A BR 8306653 A BR8306653 A BR 8306653A BR 8306653 A BR8306653 A BR 8306653A BR 8306653 A BR8306653 A BR 8306653A
- Authority
- BR
- Brazil
- Prior art keywords
- channel
- well region
- self
- defining
- definition
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
- H01L21/76218—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers introducing both types of electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers, e.g. for isolation of complementary doped regions
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/975—Substrate or mask aligning feature
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Formation Of Insulating Films (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/448,125 US4470191A (en) | 1982-12-09 | 1982-12-09 | Process for making complementary transistors by sequential implantations using oxidation barrier masking layer |
Publications (1)
Publication Number | Publication Date |
---|---|
BR8306653A true BR8306653A (pt) | 1984-07-31 |
Family
ID=23779101
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR8306653A BR8306653A (pt) | 1982-12-09 | 1983-12-02 | Processo para fazer transistores complementares |
Country Status (7)
Country | Link |
---|---|
US (1) | US4470191A (pt) |
EP (1) | EP0111098B1 (pt) |
JP (1) | JPS59111359A (pt) |
AT (1) | ATE26897T1 (pt) |
BR (1) | BR8306653A (pt) |
CA (1) | CA1191973A (pt) |
DE (1) | DE3371264D1 (pt) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4574467A (en) * | 1983-08-31 | 1986-03-11 | Solid State Scientific, Inc. | N- well CMOS process on a P substrate with double field guard rings and a PMOS buried channel |
US4839542A (en) * | 1984-08-21 | 1989-06-13 | General Datacomm Industries, Inc. | Active transconductance filter device |
US4600445A (en) * | 1984-09-14 | 1986-07-15 | International Business Machines Corporation | Process for making self aligned field isolation regions in a semiconductor substrate |
US4584027A (en) * | 1984-11-07 | 1986-04-22 | Ncr Corporation | Twin well single mask CMOS process |
US4707455A (en) * | 1986-11-26 | 1987-11-17 | General Electric Company | Method of fabricating a twin tub CMOS device |
US5132236A (en) * | 1991-07-30 | 1992-07-21 | Micron Technology, Inc. | Method of semiconductor manufacture using an inverse self-aligned mask |
US5233080A (en) * | 1992-09-25 | 1993-08-03 | E. I. Du Pont De Nemours And Company | Preparation of N-acylaminomethylphosphonic acids and aminomethylphosphonic acids |
JP3958388B2 (ja) * | 1996-08-26 | 2007-08-15 | 株式会社ルネサステクノロジ | 半導体装置 |
US5956583A (en) * | 1997-06-30 | 1999-09-21 | Fuller; Robert T. | Method for forming complementary wells and self-aligned trench with a single mask |
US6274443B1 (en) * | 1998-09-28 | 2001-08-14 | Advanced Micro Devices, Inc. | Simplified graded LDD transistor using controlled polysilicon gate profile |
US6063672A (en) * | 1999-02-05 | 2000-05-16 | Lsi Logic Corporation | NMOS electrostatic discharge protection device and method for CMOS integrated circuit |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3700507A (en) * | 1969-10-21 | 1972-10-24 | Rca Corp | Method of making complementary insulated gate field effect transistors |
NL160988C (nl) * | 1971-06-08 | 1979-12-17 | Philips Nv | Halfgeleiderinrichting met een halfgeleiderlichaam, be- vattende ten minste een eerste veldeffecttransistor met geisoleerde stuurelektrode en werkwijze voor de vervaar- diging van de halfgeleiderinrichting. |
US3999213A (en) * | 1972-04-14 | 1976-12-21 | U.S. Philips Corporation | Semiconductor device and method of manufacturing the device |
US4033797A (en) * | 1973-05-21 | 1977-07-05 | Hughes Aircraft Company | Method of manufacturing a complementary metal-insulation-semiconductor circuit |
US4027380A (en) * | 1974-06-03 | 1977-06-07 | Fairchild Camera And Instrument Corporation | Complementary insulated gate field effect transistor structure and process for fabricating the structure |
US4002501A (en) * | 1975-06-16 | 1977-01-11 | Rockwell International Corporation | High speed, high yield CMOS/SOS process |
US4045250A (en) * | 1975-08-04 | 1977-08-30 | Rca Corporation | Method of making a semiconductor device |
JPS5286083A (en) * | 1976-01-12 | 1977-07-16 | Hitachi Ltd | Production of complimentary isolation gate field effect transistor |
US4183134A (en) * | 1977-02-15 | 1980-01-15 | Westinghouse Electric Corp. | High yield processing for silicon-on-sapphire CMOS integrated circuits |
US4224733A (en) * | 1977-10-11 | 1980-09-30 | Fujitsu Limited | Ion implantation method |
US4244752A (en) * | 1979-03-06 | 1981-01-13 | Burroughs Corporation | Single mask method of fabricating complementary integrated circuits |
US4306916A (en) * | 1979-09-20 | 1981-12-22 | American Microsystems, Inc. | CMOS P-Well selective implant method |
US4382827A (en) * | 1981-04-27 | 1983-05-10 | Ncr Corporation | Silicon nitride S/D ion implant mask in CMOS device fabrication |
US4385947A (en) * | 1981-07-29 | 1983-05-31 | Harris Corporation | Method for fabricating CMOS in P substrate with single guard ring using local oxidation |
US4399605A (en) * | 1982-02-26 | 1983-08-23 | International Business Machines Corporation | Method of making dense complementary transistors |
US4412375A (en) * | 1982-06-10 | 1983-11-01 | Intel Corporation | Method for fabricating CMOS devices with guardband |
-
1982
- 1982-12-09 US US06/448,125 patent/US4470191A/en not_active Expired - Lifetime
-
1983
- 1983-07-20 JP JP58131118A patent/JPS59111359A/ja active Pending
- 1983-10-11 AT AT83110131T patent/ATE26897T1/de active
- 1983-10-11 DE DE8383110131T patent/DE3371264D1/de not_active Expired
- 1983-10-11 EP EP83110131A patent/EP0111098B1/en not_active Expired
- 1983-11-08 CA CA000440689A patent/CA1191973A/en not_active Expired
- 1983-12-02 BR BR8306653A patent/BR8306653A/pt unknown
Also Published As
Publication number | Publication date |
---|---|
US4470191A (en) | 1984-09-11 |
DE3371264D1 (en) | 1987-06-04 |
EP0111098B1 (en) | 1987-04-29 |
EP0111098A1 (en) | 1984-06-20 |
JPS59111359A (ja) | 1984-06-27 |
CA1191973A (en) | 1985-08-13 |
ATE26897T1 (de) | 1987-05-15 |
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