EP0111098A1 - Method of making complementary metal oxide semiconductor structures - Google Patents

Method of making complementary metal oxide semiconductor structures Download PDF

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Publication number
EP0111098A1
EP0111098A1 EP83110131A EP83110131A EP0111098A1 EP 0111098 A1 EP0111098 A1 EP 0111098A1 EP 83110131 A EP83110131 A EP 83110131A EP 83110131 A EP83110131 A EP 83110131A EP 0111098 A1 EP0111098 A1 EP 0111098A1
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Prior art keywords
layer
set forth
silicon
well
channel
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EP83110131A
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German (de)
French (fr)
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EP0111098B1 (en
Inventor
Peter Edwin Cottrell
Henry John Geipel, Jr.
Donald Mcalpine Kenney
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H01L21/76218—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers introducing both types of electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers, e.g. for isolation of complementary doped regions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/975—Substrate or mask aligning feature

Definitions

  • This invention relates to a process for making dense integrated semiconductor structures and, more particularly, to a process for making an array of transistors in the complementary metal oxide semiconductor (CMOS) technology wherein both N and P channel transistors are formed on a common semiconductor substrate.
  • CMOS complementary metal oxide semiconductor
  • CMOS technology provides certain advantages over integrated semiconductor technologies that use only N channel devices or P channel devices. Some of these advantages include speed and virtually no standby power.
  • the method includes applying a photoresist layer over the insulating layer with an opening over one of the thin insulating films, introducing a first impurity into the channel region of the one portion to adjust the impurity therein and depositing a first conductive material on the thin insulating film located over the channel region of the one portion.
  • the photoresist layer is then removed and a second impurity is introduced into the channel region of the other portion to adjust the impurity therein.
  • a second conductive material is deposited on the thin insulating film located over the channel region of the other portion and in contact with the first conductive material, with the second conductive material having a different work function than that of the first conductive material.
  • the first conductive material is, preferably, platinum silicide while the second conductive material may be aluminum.
  • the invention as claimed is intended to provide a simple process for making a very planar CMOS structure with tight geometries which has well and field regions self-aligned to each other after the active device regions have been defined.
  • CMOS structure wherein isolation regions required by bulk CMOS structures are first formed, an N channel device field region is self-aligned to an N well region in a semiconductor substrate and a polysilicon layer, or other refractory material, is twice defined for forming P and N channels, the first definition masking P channel source and drain regions while defining the N channel and the second definition defining the P channel while using a photoresist layer to mask the N channel.
  • a single mask level defines the well region and self-aligns the necessary field doping to the well region to provide closely spaced N and P channel devices.
  • Fig. 1 a sectional view of the CMOS structure made in accordance with the process of the present invention during an early stage of the fabrication thereof.
  • the structure includes a semiconductor substrate 10, which is made of a P+ conductivity type silicon and an epitaxial semiconductor layer 12, preferably P- type silicon, grown on substrate 10.
  • a thin layer of silicon dioxide 14 is grown on the epitaxial layer 12 and a layer of silicon nitride 16 is deposited, preferably by known low pressure chemical vapor deposition techniques, on the silicon dioxide layer 14.
  • a first layer 18 of polysilicon which may have a thickness of 150 nanometers, is deposited on the silicon nitride layer 16 by any known technique, preferably, by undoped low pressure chemical vapor deposition.
  • the thickness of the epitaxial silicon layer 12 may be from 1 to 15 micrometers and have a resistivity range from 5 to 50 ohm-centimeters, and the layers 14 and 16 may have a thickness of 40 and 100 nanometers, respectively.
  • openings 20, 22 and 24 are formed in the polysilicon and silicon nitride layers 16 and 18 to define pads 26 and 28 for semi-recessed oxide segments 30, 32 and 34, illustrated in Fig. 3 of the drawings.
  • the first polysilicon layer 18 and the silicon nitride layer 16 may be dry etched by the use of carbon tetrafluoride (CF 4 ) and oxygen gas.
  • CF 4 carbon tetrafluoride
  • the photoresist mask is then stripped in an oxygen plasma and the surface of the remaining structure cleaned by any known process.
  • a second photoresist mask 36 illustrated in Fig. 2, is provided over the first polysilicon layer 18 and the exposed surfaces of the silicon dioxide layer 14 having an opening 38 to define an N well 40, wherein phosphorous ions are implanted.
  • a second layer of polysilicon is, preferably, directionally evaporated over the second photoresist mask 36 and into the opening 38 forming first and second polysilicon segments 42 and 44, respectively.
  • This polysilicon layer may be semi-crystalline or amorphous at this point in the process.
  • the segment 42 of the second polysilicon layer deposited over the second photoresist mask 36 is removed, along with the second photoresist mask 36, by known lift-off techniques, and the phosphorous ions are driven deeper into epitaxial layer 12 by a known heat process in an inert atmosphere.
  • boron is implanted into selected portions of the surface of the P- epitaxial layer 12 defined by the pad 28 and polysilicon segment 44 for providing N channel device field regions 46 and 48, indicated in Fig. 3. All remaining polysilicon is now stripped and the semi-recessed oxide regions 30, 32 and 34 are grown adjacent to thin silicon dioxide regions 14' and 14" which have been protected by the silicon nitride layer 16 in pads 26 and 28. The pads 26 and 28 are then stripped, gate insulators, such as 14' and 14", are regrown and a boron channel implant is performed.
  • a third layer of polysilicon is deposited over the thin silicon dioxide regions 14' and 14" and the recessed oxide regions 30, 32 and 34 and appropriately selectively etched with the use of a third photoresist mask, not shown, to form a first segment for use as a first gate electrode 50 of a first device 52 and a second segment 54 for use as an ion mask to protect the N well 40.
  • Arsenic ions are implanted to form N+ source and drain regions 56 and 58 for the first device 52, followed by a heating step to partially drive in the arsenic ions.
  • a fourth photoresist mask 60 has openings 62 and 64 for defining in second polysilicon segment 54 a second gate electrode 66 of a second device 68.
  • the exposed polysilicon in segment 54 is etched away to form the electrode 66 shown in Fig. 5.
  • Mask 60 is also arranged as an ion barrier to protect device 52 when boron is implanted to form P+ source and drain regions 70 and 72 of the second device 68. After the boron has been implanted, the mask 60 is stripped and the remaining polysilicon, i.e., first and second gate electrodes 50 and 66 have their surfaces oxidized to form silicon dioxide layers 73 and 74, respectively, as illustrated in Fig. 6 of the drawings, with the implanted ions being further driven into the epitaxial layer 12.
  • Any appropriate passifying layer such as phosphosilicate glass, may now be provided over the surface of the structure and appropriate contact holes defined and opened with the use of a fifth photoresist mask, not shown.
  • a metal layer e.g., copper-doped aluminum, is deposited over the passifying layer and into the openings and etched so as to form contacts such as gate electrode contacts 76 and 78 for gate electrodes 50 and 66, respectively, and source/drain region contacts such as 80 and 82.
  • CMOS structure with tight geometries which uses a lift-off technique to form a self-aligned P type field region for an N channel device and an N type P channel device well region.
  • a refractory material such as polysilicon permits the N well to be driven in with the reversed N well mask in place.
  • the field oxide is defined with a conventional oxidizing barrier material, while the polysilicon gate electrode layer is used as a mask and is twice defined to form the gate electrodes for the N channel and P channel transistors 52 and 68.
  • the first definition leaves the N channel gate electrode and the P channel gate electrode and diffusion regions covered or protected by the polysilicon layer, and the second definition leaves polysilicon over only the P channel and N channel gate electrodes of transistors 52 and 68, with a photoresist mask covering the diffusion regions of transistor 52.
  • the threshold of the P channel transistor is generally too negative in this structure in view of the work function of N+ polysilicon used to form the gate electrode 66.
  • N channel boron channel implant the threshold is increased toward zero volts.
  • the threshold may be further controlled by the use of multiple implants when forming the N well. Implants of different energies allow independent control of the well depth and surface doping. A deep well with a relatively low surface doping also serves to move the P channel threshold toward zero and aids in latch-up prevention by the use of the retrograde well.
  • the P channel threshold is lowered while the N channel threshold is raised to provide near optimum threshold values in a CMOS structure.

Abstract

A simple process is provided for making a planar CMOS structure wherein isolation regions required by bulk CMOS structures are first formed, an N channel device field region is self-aligned to an N well region in a semiconductor substrate and a refractory material is twice defined for forming P and N channels, the first definition masking P channel source and drain regions while defining the N channel and the second definition defining the P channel while using a photoresist layer to mask the N channel. In the process, a technique which uses a single mask level defines the well region and self-aligns the necessary field doping to the well region to provide closely spaced N and P channel devices.

Description

  • This invention relates to a process for making dense integrated semiconductor structures and, more particularly, to a process for making an array of transistors in the complementary metal oxide semiconductor (CMOS) technology wherein both N and P channel transistors are formed on a common semiconductor substrate.
  • It is well known that the CMOS technology provides certain advantages over integrated semiconductor technologies that use only N channel devices or P channel devices. Some of these advantages include speed and virtually no standby power.
  • Processes for providing CMOS devices are taught in, e.g., U.S. Patents 4 002 501, filed June 16, 1975, and 4 183 134, filed December 11, 1978. These patents teach processes for making complementary devices which have controlled channel lengths and low gate overlap capacitance by the use of thick insulators over their source and drain regions.
  • Other processes and structures known in the CMOS technology are taught in U.S. Patent 4 045 250, filed August 4, 1975, which discloses a process for producing a CMOS structure having a process step wherein a single oxidation step grows relatively thick isolation and source/drain passivation concurrently, and in U.S. Patent 3 700 507, filed October 21, 1969, which discloses a method of making CMOS structures with a reduced number of heat treatment steps.
  • In U.S. Patent 4 244 752, filed March 6, 1979, there is described a method of fabricating complementary integrated circuits which includes a technique for twice defining a gate polysilicon to form the P and N channel gates.
  • In commonly assigned U.S. patent application having Serial No. 352 990, filed on February 26, 1982, by S. Dash et al, there is described a method of making complementary field effect transistors in a semiconductor layer formed on an insulator having a first portion which includes an N type transistor with a channel region defined by N+ source and drain regions and having a second portion including a P type transistor with a channel region defined by P+ source and drain regions. An insulating layer is disposed over the first and second portions with thin insulating films formed only over the channel regions. The method includes applying a photoresist layer over the insulating layer with an opening over one of the thin insulating films, introducing a first impurity into the channel region of the one portion to adjust the impurity therein and depositing a first conductive material on the thin insulating film located over the channel region of the one portion. The photoresist layer is then removed and a second impurity is introduced into the channel region of the other portion to adjust the impurity therein. A second conductive material is deposited on the thin insulating film located over the channel region of the other portion and in contact with the first conductive material, with the second conductive material having a different work function than that of the first conductive material. The first conductive material is, preferably, platinum silicide while the second conductive material may be aluminum.
  • In another commonly assigned U.S. patent application having Serial No. 446 793, entitled, "Method of Making High Density Complementary Transistors", filed by H. J. Geipel, Jr., R. R. Troutman and J. M. Wursthorn on December 3, 1982, there is described a method of making complementary field effect transistors in an N type conductivity semiconductor layer which includes forming a well having a P type conductivity in the semiconductor layer and forming first and second N type conductivity regions defining a channel region within the well. A P type conductivity region is then formed within the well surrounding the first and second N type conductivity regions and the channel region, followed by the formation of a P channel device in the semiconductor layer outside of the P type well.
  • The invention as claimed is intended to provide a simple process for making a very planar CMOS structure with tight geometries which has well and field regions self-aligned to each other after the active device regions have been defined.
  • In accordance with the teachings of this invention, a simple process is provided for making a planar CMOS structure wherein isolation regions required by bulk CMOS structures are first formed, an N channel device field region is self-aligned to an N well region in a semiconductor substrate and a polysilicon layer, or other refractory material, is twice defined for forming P and N channels, the first definition masking P channel source and drain regions while defining the N channel and the second definition defining the P channel while using a photoresist layer to mask the N channel. In the process a single mask level defines the well region and self-aligns the necessary field doping to the well region to provide closely spaced N and P channel devices.
  • The foregoing and other objects, features and advantages of the invention will be apparent from the following and more particular description of the preferred embodiments of the invention, as illustrated in the accompanying drawings, in which
    • Figs. 1-6 are sectional views of the CMOS structure made after successive steps during the process of the present invention.
  • Referring to the drawings in more detail, there is illustrated in Fig. 1 a sectional view of the CMOS structure made in accordance with the process of the present invention during an early stage of the fabrication thereof. The structure includes a semiconductor substrate 10, which is made of a P+ conductivity type silicon and an epitaxial semiconductor layer 12, preferably P- type silicon, grown on substrate 10. A thin layer of silicon dioxide 14 is grown on the epitaxial layer 12 and a layer of silicon nitride 16 is deposited, preferably by known low pressure chemical vapor deposition techniques, on the silicon dioxide layer 14. A first layer 18 of polysilicon, which may have a thickness of 150 nanometers, is deposited on the silicon nitride layer 16 by any known technique, preferably, by undoped low pressure chemical vapor deposition. The thickness of the epitaxial silicon layer 12 may be from 1 to 15 micrometers and have a resistivity range from 5 to 50 ohm-centimeters, and the layers 14 and 16 may have a thickness of 40 and 100 nanometers, respectively.
  • With a first conventional photoresist mask, not shown, openings 20, 22 and 24 are formed in the polysilicon and silicon nitride layers 16 and 18 to define pads 26 and 28 for semi-recessed oxide segments 30, 32 and 34, illustrated in Fig. 3 of the drawings. The first polysilicon layer 18 and the silicon nitride layer 16 may be dry etched by the use of carbon tetrafluoride (CF4) and oxygen gas. The photoresist mask is then stripped in an oxygen plasma and the surface of the remaining structure cleaned by any known process.
  • A second photoresist mask 36, illustrated in Fig. 2, is provided over the first polysilicon layer 18 and the exposed surfaces of the silicon dioxide layer 14 having an opening 38 to define an N well 40, wherein phosphorous ions are implanted. The edge of the mask 36, as indicated at opening 38, has a reentrant slope. A second layer of polysilicon is, preferably, directionally evaporated over the second photoresist mask 36 and into the opening 38 forming first and second polysilicon segments 42 and 44, respectively. This polysilicon layer may be semi-crystalline or amorphous at this point in the process. The segment 42 of the second polysilicon layer deposited over the second photoresist mask 36 is removed, along with the second photoresist mask 36, by known lift-off techniques, and the phosphorous ions are driven deeper into epitaxial layer 12 by a known heat process in an inert atmosphere.
  • With the segment 44 of the polysilicon layer in place, boron is implanted into selected portions of the surface of the P- epitaxial layer 12 defined by the pad 28 and polysilicon segment 44 for providing N channel device field regions 46 and 48, indicated in Fig. 3. All remaining polysilicon is now stripped and the semi-recessed oxide regions 30, 32 and 34 are grown adjacent to thin silicon dioxide regions 14' and 14" which have been protected by the silicon nitride layer 16 in pads 26 and 28. The pads 26 and 28 are then stripped, gate insulators, such as 14' and 14", are regrown and a boron channel implant is performed.
  • As indicated in Fig. 4 of the drawings, a third layer of polysilicon is deposited over the thin silicon dioxide regions 14' and 14" and the recessed oxide regions 30, 32 and 34 and appropriately selectively etched with the use of a third photoresist mask, not shown, to form a first segment for use as a first gate electrode 50 of a first device 52 and a second segment 54 for use as an ion mask to protect the N well 40. Arsenic ions are implanted to form N+ source and drain regions 56 and 58 for the first device 52, followed by a heating step to partially drive in the arsenic ions.
  • A fourth photoresist mask 60 has openings 62 and 64 for defining in second polysilicon segment 54 a second gate electrode 66 of a second device 68. The exposed polysilicon in segment 54 is etched away to form the electrode 66 shown in Fig. 5. Mask 60 is also arranged as an ion barrier to protect device 52 when boron is implanted to form P+ source and drain regions 70 and 72 of the second device 68. After the boron has been implanted, the mask 60 is stripped and the remaining polysilicon, i.e., first and second gate electrodes 50 and 66 have their surfaces oxidized to form silicon dioxide layers 73 and 74, respectively, as illustrated in Fig. 6 of the drawings, with the implanted ions being further driven into the epitaxial layer 12.
  • Any appropriate passifying layer, such as phosphosilicate glass, may now be provided over the surface of the structure and appropriate contact holes defined and opened with the use of a fifth photoresist mask, not shown. A metal layer, e.g., copper-doped aluminum, is deposited over the passifying layer and into the openings and etched so as to form contacts such as gate electrode contacts 76 and 78 for gate electrodes 50 and 66, respectively, and source/drain region contacts such as 80 and 82.
  • Although the process has been described in the above embodiment in which an N well is formed in a P- epitaxial layer, it should be understood that the process may be modified within the scope of this invention by, e.g., forming a P well in an N type epitaxial layer. Also, other known barrier materials, insulating materials or dopants than those mentioned hereinabove may be used to practice this invention, as is known to those skilled in the art.
  • It can be seen that a simple process has been provided for making an integrated circuit CMOS structure with tight geometries which uses a lift-off technique to form a self-aligned P type field region for an N channel device and an N type P channel device well region. A refractory material such as polysilicon permits the N well to be driven in with the reversed N well mask in place. The field oxide is defined with a conventional oxidizing barrier material, while the polysilicon gate electrode layer is used as a mask and is twice defined to form the gate electrodes for the N channel and P channel transistors 52 and 68. The first definition leaves the N channel gate electrode and the P channel gate electrode and diffusion regions covered or protected by the polysilicon layer, and the second definition leaves polysilicon over only the P channel and N channel gate electrodes of transistors 52 and 68, with a photoresist mask covering the diffusion regions of transistor 52.
  • It should be noted further that the threshold of the P channel transistor is generally too negative in this structure in view of the work function of N+ polysilicon used to form the gate electrode 66. By using an N channel boron channel implant the threshold is increased toward zero volts. Accordingly, it can be seen that a wiring advantage is provided since the N channel and P channel gate electrodes of CMOS devices are formed from the same polysilicon material. Of course, the threshold may be further controlled by the use of multiple implants when forming the N well. Implants of different energies allow independent control of the well depth and surface doping. A deep well with a relatively low surface doping also serves to move the P channel threshold toward zero and aids in latch-up prevention by the use of the retrograde well. By adjusting the P channel threshold simultaneously with the N channel by a boron channel implant, the P channel threshold is lowered while the N channel threshold is raised to provide near optimum threshold values in a CMOS structure.

Claims (16)

1. A method of making a complementary metal oxide semiconductor (CMOS) structure, characterized by comprising the steps of:
forming an oxidation barrier layer (16) on a semiconductor substrate (12) of a given conductivity type,
defining an isolation region (32) having first and second ends in said substrate (12),
removing a portion of said oxidation barrier layer (16) over said isolation region (32),
defining with a first ion implant masking layer (36) a well (40) in said substrate (12) extending from within the first end of said isolation region (32),
implanting a first impurity having a conductivity type opposite to that of said given conductivity type into said well (40),
masking said well (40) with a second ion implant masking layer (44),
removing said first masking layer (36),
implanting a second impurity having said given conductivity type into said substrate (12) without said well (40) to the second end of said isolation region (32), removing said second masking layer (44), and
oxidizing the surface of said substrate (12) without the remaining portion of said oxidation barrier layer (16).
2. A method a set forth in Claim 1 wherein an edge of said well (40) is disposed between and at a substantial distance from the first and second ends of said isolation region (32).
3. A method as set forth in Claim 2 wherein said second impurity is implanted into said substrate (12) between the edge of said well (40) and the second end of said isolation region (32) to form a field region (46).
4. A method as set forth in Claim 3 wherein said field region (46) butts said N well (40).
5. A method as set forth in Claim 3 wherein said oxidation barrier layer (16) is a refractory material.
6. A method as set forth in Claim 5 wherein said oxidation barrier layer (16) includes silicon nitride.
7. A method as set forth in Claim 3 wherein said second ion implant masking layer (44) is a refractory material.
8. A method as set forth in Claim 7 wherein said refractory material is silicon.
9. A method as set forth in Claim 1 wherein said first ion implant masking layer (36) is a photoresist layer.
10. A method as set forth in Claim 5 further including the step of forming a layer of polysilicon (18) over said refractory material.
11. A method as set forth in Claim 1 wherein said substrate (12) is annealed after said first impurity is implanted and before said second impurity is implanted.
12. A method as set forth in Claim 1 further including the step of annealing said substrate (12) after said first and second impurities are implanted.
13. A method as set forth in Claim 1 wherein said first ion implant masking layer (36) has a reentrant slope.
14. A method as set forth in Claims 8 and 9 wherein said second silicon layer (44) is deposited over said well (40) and over said photoresist layer (36) and then the portion of said second silicon layer (44) disposed over said photoresist layer (36) is removed with said photoresist layer.
15. A method as set forth in Claim 14 wherein the thickness of said second silicon layer (44, 42) is less than that of said photoresist layer (36), said N type impurity is phosphorous and said P type impurity is boron.
16. A process for making a semiconductor structure as claimed in Claims 1 to 14 comprising the steps of:
growing a layer of silicon dioxide (14) on an epitaxial semiconductor layer (12) having a given P type conductivity,
depositing a layer of silicon nitride (16) on said silicon dioxide layer (14),
depositing a first layer of silicon (18) on said silicon nitride layer (16),
forming openings (20, 22, 24) in said silicon (18) and silicon dioxide layers to define an isolation region (30, 32, 34) in the surface of said epitaxial semiconductor layer (12),
depositing a layer of photoresist over said silicon layer (18) and in said openings (20, 22, 24),
removing said photoresist layer from a point within one of said openings (22) to a point within an adjacent opening (24) with the edge of said photoresist layer (36) having a reentrant slope,
implanting an N type impurity into said epitaxial semiconductor layer (12) without the remaining portion (36) of said photoresist layer to form an N well (40),
depositing a second layer of silicon (44, 42) over the remaining portion of said photoresist layer (36) and over said N well (40),
removing the remaining portion of said photoresist layer (36) and the portion of said second silicon layer (42) thereover,
implanting a P type impurity into said epitaxial semiconductor layer (12) between the end of said N well (40) and an edge of said layer of silicon nitride (22) to form a field region (46) having a higher P type conductivity than said given P type conductivity,
removing the remaining portions of said first and second silicon layers (18, 44), and
oxidizing the surface of said epitaxial layer (12) outside of the remaining portion of said silicon nitride layer (16) to form semi-recessed silicon dioxide segments (30, 32, 34) in said epitaxial layer (12).
EP83110131A 1982-12-09 1983-10-11 Method of making complementary metal oxide semiconductor structures Expired EP0111098B1 (en)

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AT83110131T ATE26897T1 (en) 1982-12-09 1983-10-11 METHOD OF MAKING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR STRUCTURES.

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US448125 1982-12-09
US06/448,125 US4470191A (en) 1982-12-09 1982-12-09 Process for making complementary transistors by sequential implantations using oxidation barrier masking layer

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EP0111098A1 true EP0111098A1 (en) 1984-06-20
EP0111098B1 EP0111098B1 (en) 1987-04-29

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EP0178418A2 (en) * 1984-09-14 1986-04-23 International Business Machines Corporation Process for making a semiconductor structure

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ATE26897T1 (en) 1987-05-15
DE3371264D1 (en) 1987-06-04
US4470191A (en) 1984-09-11
BR8306653A (en) 1984-07-31
JPS59111359A (en) 1984-06-27
CA1191973A (en) 1985-08-13
EP0111098B1 (en) 1987-04-29

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