BR112019005111A2 - solução de chip dividido para serdes de matriz-a-matriz - Google Patents

solução de chip dividido para serdes de matriz-a-matriz

Info

Publication number
BR112019005111A2
BR112019005111A2 BR112019005111A BR112019005111A BR112019005111A2 BR 112019005111 A2 BR112019005111 A2 BR 112019005111A2 BR 112019005111 A BR112019005111 A BR 112019005111A BR 112019005111 A BR112019005111 A BR 112019005111A BR 112019005111 A2 BR112019005111 A2 BR 112019005111A2
Authority
BR
Brazil
Prior art keywords
matrix
services
split
chip solution
integrated circuit
Prior art date
Application number
BR112019005111A
Other languages
English (en)
Other versions
BR112019005111B1 (pt
Inventor
Terzioglu Esin
Gilberto Corleto Mena Jose
Allam Mohamed
Kong Xiaohua
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112019005111A2 publication Critical patent/BR112019005111A2/pt
Publication of BR112019005111B1 publication Critical patent/BR112019005111B1/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Theoretical Computer Science (AREA)
  • Electromagnetism (AREA)
  • Nonlinear Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Information Transfer Systems (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

é fornecido um pacote de circuito integrado de soc no qual os componentes analógicos de um serdes para uma matriz de soc no pacote de circuito integrado de soc são segregados em uma matriz de interface de serdes no pacote de circuito integrado de soc.
BR112019005111-2A 2016-09-22 2017-08-30 Solução de chip dividido para serdes de matriz-a-matriz BR112019005111B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/273,621 US9692448B1 (en) 2016-09-22 2016-09-22 Split chip solution for die-to-die serdes
US15/273,621 2016-09-22
PCT/US2017/049487 WO2018057259A1 (en) 2016-09-22 2017-08-30 Split chip solution for die-to-die serdes

Publications (2)

Publication Number Publication Date
BR112019005111A2 true BR112019005111A2 (pt) 2019-06-04
BR112019005111B1 BR112019005111B1 (pt) 2023-12-05

Family

ID=59070349

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112019005111-2A BR112019005111B1 (pt) 2016-09-22 2017-08-30 Solução de chip dividido para serdes de matriz-a-matriz

Country Status (7)

Country Link
US (1) US9692448B1 (pt)
EP (1) EP3516689B1 (pt)
JP (1) JP6657481B2 (pt)
KR (1) KR101995562B1 (pt)
CN (1) CN109791928B (pt)
BR (1) BR112019005111B1 (pt)
WO (1) WO2018057259A1 (pt)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10090993B2 (en) * 2016-08-19 2018-10-02 Ali Corporation Packaged circuit
US11460875B2 (en) * 2018-12-17 2022-10-04 Marvell Asia Pte Ltd. Bandgap circuits with voltage calibration
CN112732631A (zh) * 2020-12-25 2021-04-30 南京蓝洋智能科技有限公司 一种小芯片间的数据传输方法
US20230305737A1 (en) * 2022-03-22 2023-09-28 Silicon Laboratories Inc. External Nonvolatile Memory with Additional Functionality

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7227918B2 (en) * 2000-03-14 2007-06-05 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry
US7496818B1 (en) 2003-02-27 2009-02-24 Marvell International Ltd. Apparatus and method for testing and debugging an integrated circuit
US7342310B2 (en) 2004-05-07 2008-03-11 Avago Technologies General Ip Pte Ltd Multi-chip package with high-speed serial communications between semiconductor die
US20070194453A1 (en) * 2006-01-27 2007-08-23 Kanad Chakraborty Integrated circuit architecture for reducing interconnect parasitics
US8595672B2 (en) 2007-04-30 2013-11-26 Innovations Holdings, L.L.C. Method and apparatus for configurable systems
US8890332B2 (en) * 2010-07-29 2014-11-18 Mosys, Inc. Semiconductor chip layout with staggered Tx and Tx data lines
US8730978B2 (en) * 2010-09-30 2014-05-20 Maxim Integrated Products, Inc Analog front end protocol converter/adapter for SLPI protocol
US8832487B2 (en) 2011-06-28 2014-09-09 Microsoft Corporation High-speed I/O data system
US8626975B1 (en) * 2011-09-28 2014-01-07 Maxim Integrated Products, Inc. Communication interface with reduced signal lines
US9971730B2 (en) 2014-06-16 2018-05-15 Qualcomm Incorporated Link layer to physical layer (PHY) serial interface
US9607948B2 (en) * 2015-03-31 2017-03-28 Xilinx, Inc. Method and circuits for communication in multi-die packages

Also Published As

Publication number Publication date
EP3516689C0 (en) 2024-01-24
JP2019537841A (ja) 2019-12-26
BR112019005111B1 (pt) 2023-12-05
US9692448B1 (en) 2017-06-27
KR101995562B1 (ko) 2019-07-02
CN109791928B (zh) 2020-02-07
KR20190037338A (ko) 2019-04-05
WO2018057259A1 (en) 2018-03-29
CN109791928A (zh) 2019-05-21
JP6657481B2 (ja) 2020-03-04
EP3516689A1 (en) 2019-07-31
EP3516689B1 (en) 2024-01-24

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Legal Events

Date Code Title Description
B350 Update of information on the portal [chapter 15.35 patent gazette]
B06W Patent application suspended after preliminary examination (for patents with searches from other patent authorities) chapter 6.23 patent gazette]
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 30/08/2017, OBSERVADAS AS CONDICOES LEGAIS