BR112018004715A2 - sistemas unificados e métodos para comunicação de nó entre chips e interna de chip - Google Patents

sistemas unificados e métodos para comunicação de nó entre chips e interna de chip

Info

Publication number
BR112018004715A2
BR112018004715A2 BR112018004715A BR112018004715A BR112018004715A2 BR 112018004715 A2 BR112018004715 A2 BR 112018004715A2 BR 112018004715 A BR112018004715 A BR 112018004715A BR 112018004715 A BR112018004715 A BR 112018004715A BR 112018004715 A2 BR112018004715 A2 BR 112018004715A2
Authority
BR
Brazil
Prior art keywords
node
chip
chips
message
methods
Prior art date
Application number
BR112018004715A
Other languages
English (en)
Portuguese (pt)
Inventor
Alan Wiley George
Leclercq Maxime
Dominic Wietfeldt Richard
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112018004715A2 publication Critical patent/BR112018004715A2/pt

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4027Coupling between buses using bus bridges
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/382Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4022Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4063Device-to-bus coupling
    • G06F13/4068Electrical coupling
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00Arrangements for monitoring or testing data switching networks
    • H04L43/08Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0805Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability
    • H04L43/0817Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability by checking functioning

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Environmental & Geological Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • Mathematical Physics (AREA)
  • Small-Scale Networks (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Bus Control (AREA)
BR112018004715A 2015-09-10 2016-08-12 sistemas unificados e métodos para comunicação de nó entre chips e interna de chip BR112018004715A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/850,104 US20170075843A1 (en) 2015-09-10 2015-09-10 Unified systems and methods for interchip and intrachip node communication
PCT/US2016/046728 WO2017044247A1 (en) 2015-09-10 2016-08-12 Unified systems and methods for interchip and intrachip node communication

Publications (1)

Publication Number Publication Date
BR112018004715A2 true BR112018004715A2 (pt) 2018-09-25

Family

ID=56787712

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018004715A BR112018004715A2 (pt) 2015-09-10 2016-08-12 sistemas unificados e métodos para comunicação de nó entre chips e interna de chip

Country Status (7)

Country Link
US (2) US20170075843A1 (enExample)
EP (2) EP4195058B1 (enExample)
JP (1) JP6845224B2 (enExample)
KR (2) KR102853457B1 (enExample)
CN (1) CN108027792B (enExample)
BR (1) BR112018004715A2 (enExample)
WO (1) WO2017044247A1 (enExample)

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US20170075843A1 (en) 2015-09-10 2017-03-16 Qualcomm Incorporated Unified systems and methods for interchip and intrachip node communication
US10521392B2 (en) 2017-05-10 2019-12-31 Qualcomm Incorporated Slave master-write/read datagram payload extension
US20190227971A1 (en) * 2018-01-23 2019-07-25 Qualcomm Incorporated Architecture for consolidating multiple sources of low-bandwidth data over a serial bus
US11443713B2 (en) * 2020-01-30 2022-09-13 Apple Inc. Billboard for context information sharing
CN113296479B (zh) * 2020-06-17 2024-07-23 盒马(中国)有限公司 总线入网单元、输送线电气控制系统及部署方法
US11675713B2 (en) 2021-04-02 2023-06-13 Micron Technology, Inc. Avoiding deadlock with a fabric having multiple systems on chip
JP2024120116A (ja) * 2021-05-10 2024-09-04 日本たばこ産業株式会社 エアロゾル生成装置の回路ユニット及びエアロゾル生成装置
CN115460128B (zh) * 2022-11-09 2023-07-07 之江实验室 一种面向多芯粒组合芯片的片上网络仿真系统

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US20070109015A1 (en) * 2005-11-15 2007-05-17 Alcatel Switched integrated circuit connection architectures and techniques
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Also Published As

Publication number Publication date
US20170075843A1 (en) 2017-03-16
KR20180050727A (ko) 2018-05-15
US11720512B2 (en) 2023-08-08
EP4195058A1 (en) 2023-06-14
JP2018528540A (ja) 2018-09-27
CN108027792A (zh) 2018-05-11
KR102704511B1 (ko) 2024-09-06
KR102853457B1 (ko) 2025-09-01
EP4195058C0 (en) 2024-07-03
JP6845224B2 (ja) 2021-03-17
CN108027792B (zh) 2021-08-20
WO2017044247A1 (en) 2017-03-16
KR20240108580A (ko) 2024-07-09
EP4195058B1 (en) 2024-07-03
US20210326290A1 (en) 2021-10-21
EP3347823A1 (en) 2018-07-18

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Legal Events

Date Code Title Description
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09B Patent application refused [chapter 9.2 patent gazette]
B12B Appeal against refusal [chapter 12.2 patent gazette]