BR112018004288A2 - advanced node chip (soc) system inductor integration using inductor glass blade and blade to blade junction - Google Patents

advanced node chip (soc) system inductor integration using inductor glass blade and blade to blade junction

Info

Publication number
BR112018004288A2
BR112018004288A2 BR112018004288-9A BR112018004288A BR112018004288A2 BR 112018004288 A2 BR112018004288 A2 BR 112018004288A2 BR 112018004288 A BR112018004288 A BR 112018004288A BR 112018004288 A2 BR112018004288 A2 BR 112018004288A2
Authority
BR
Brazil
Prior art keywords
wafer
inductor
soc
vias
magnetic layer
Prior art date
Application number
BR112018004288-9A
Other languages
English (en)
Portuguese (pt)
Inventor
Arabi Karim
Vaman Shenoy Ravindra
Petrovich Gousev Evgeni
Erturk Mete
Original Assignee
Qualcomm Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Publication of BR112018004288A2 publication Critical patent/BR112018004288A2/en

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00Resistors, capacitors or inductors
    • H10D1/20Inductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00Electrical arrangements for controlling or matching impedance
    • H10W44/501Inductive arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/401Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63Vias, e.g. via plugs
    • H10W70/635Through-vias
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68Shapes or dispositions thereof
    • H10W70/685Shapes or dispositions thereof comprising multiple insulating layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • H10W72/07231Techniques
    • H10W72/07236Soldering or alloying
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221Structures or relative sizes
    • H10W72/222Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251Materials
    • H10W72/252Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251Materials
    • H10W72/255Materials of outermost layers of multilayered bumps, e.g. material of a coating
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/728Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked discrete passive device, e.g. resistors, capacitors or inductors

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
BR112018004288-9A 2015-09-02 2016-08-08 advanced node chip (soc) system inductor integration using inductor glass blade and blade to blade junction BR112018004288A2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/843,964 2015-09-02
US14/843,964 US20170062398A1 (en) 2015-09-02 2015-09-02 Integration of inductors with advanced-node system-on-chip (soc) using glass wafer with inductors and wafer-to-wafer joining
PCT/US2016/045998 WO2017039962A1 (en) 2015-09-02 2016-08-08 Integration of inductors with advanced-node system-on-chip (soc) using glass wafer with inductors and wafer-to-wafer joining

Publications (1)

Publication Number Publication Date
BR112018004288A2 true BR112018004288A2 (en) 2018-10-09

Family

ID=56684312

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018004288-9A BR112018004288A2 (en) 2015-09-02 2016-08-08 advanced node chip (soc) system inductor integration using inductor glass blade and blade to blade junction

Country Status (8)

Country Link
US (2) US20170062398A1 (https=)
EP (1) EP3345218B1 (https=)
JP (1) JP2018532260A (https=)
KR (1) KR102541387B1 (https=)
CN (1) CN108012565A (https=)
BR (1) BR112018004288A2 (https=)
CA (1) CA2992855A1 (https=)
WO (1) WO2017039962A1 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9935076B1 (en) * 2015-09-30 2018-04-03 Apple Inc. Structure and method for fabricating a computing system with an integrated voltage regulator module
US20170169934A1 (en) * 2015-12-15 2017-06-15 Globalfoundries Inc. Patterned magnetic shields for inductors and transformers
US20200203067A1 (en) * 2017-09-29 2020-06-25 Intel Corporation Magnetic core/shell particles for inductor arrays
US11538617B2 (en) 2018-06-29 2022-12-27 Intel Corporation Integrated magnetic core inductors on glass core substrates
US11855124B2 (en) * 2019-11-15 2023-12-26 Qualcomm Incorporated Vertically integrated device stack including system on chip and power management integrated circuit
US11450628B2 (en) * 2019-12-15 2022-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure including a solenoid inductor laterally aside a die and method of fabricating the same
KR102949699B1 (ko) 2020-02-19 2026-04-10 삼성전자주식회사 반도체 패키지

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6240622B1 (en) * 1999-07-09 2001-06-05 Micron Technology, Inc. Integrated circuit inductors
US6531945B1 (en) * 2000-03-10 2003-03-11 Micron Technology, Inc. Integrated circuit inductor with a magnetic core
US6992871B2 (en) * 2003-08-06 2006-01-31 Micron Technology, Inc. Microtransformer for system-on-chip power supply
US20060088971A1 (en) * 2004-10-27 2006-04-27 Crawford Ankur M Integrated inductor and method of fabrication
US7463131B1 (en) * 2005-01-24 2008-12-09 National Semiconductor Corporation Patterned magnetic layer on-chip inductor
JP4929857B2 (ja) * 2006-06-12 2012-05-09 株式会社日立製作所 半導体装置
US9105627B2 (en) * 2011-11-04 2015-08-11 International Business Machines Corporation Coil inductor for on-chip or on-chip stack
US10115671B2 (en) * 2012-08-03 2018-10-30 Snaptrack, Inc. Incorporation of passives and fine pitch through via for package on package
US9041152B2 (en) * 2013-03-14 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Inductor with magnetic material
US9165791B2 (en) * 2013-10-31 2015-10-20 Qualcomm Incorporated Wireless interconnects in an interposer
US20150137342A1 (en) * 2013-11-20 2015-05-21 Marvell World Trade Ltd. Inductor/transformer outside of silicon wafer
WO2015127207A1 (en) * 2014-02-21 2015-08-27 Marvell World Trade Ltd. Method and apparatus for incorporating passive devices in an integrated passive device separate from a die
US9893141B2 (en) * 2015-02-26 2018-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Magnetic core, inductor, and method for fabricating the magnetic core

Also Published As

Publication number Publication date
WO2017039962A1 (en) 2017-03-09
KR102541387B1 (ko) 2023-06-08
CA2992855A1 (en) 2017-03-09
KR20180048948A (ko) 2018-05-10
CN108012565A (zh) 2018-05-08
US20210384292A1 (en) 2021-12-09
EP3345218B1 (en) 2025-06-25
JP2018532260A (ja) 2018-11-01
EP3345218C0 (en) 2025-06-25
US20170062398A1 (en) 2017-03-02
EP3345218A1 (en) 2018-07-11

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Legal Events

Date Code Title Description
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09B Patent application refused [chapter 9.2 patent gazette]
B12B Appeal against refusal [chapter 12.2 patent gazette]