US20170062398A1 - Integration of inductors with advanced-node system-on-chip (soc) using glass wafer with inductors and wafer-to-wafer joining - Google Patents
Integration of inductors with advanced-node system-on-chip (soc) using glass wafer with inductors and wafer-to-wafer joining Download PDFInfo
- Publication number
- US20170062398A1 US20170062398A1 US14/843,964 US201514843964A US2017062398A1 US 20170062398 A1 US20170062398 A1 US 20170062398A1 US 201514843964 A US201514843964 A US 201514843964A US 2017062398 A1 US2017062398 A1 US 2017062398A1
- Authority
- US
- United States
- Prior art keywords
- wafer
- inductor
- soc
- vias
- magnetic layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000011521 glass Substances 0.000 title claims description 7
- 230000010354 integration Effects 0.000 title abstract description 3
- 238000000034 method Methods 0.000 claims description 30
- 239000004020 conductor Substances 0.000 claims description 24
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 239000010409 thin film Substances 0.000 claims description 18
- 238000007747 plating Methods 0.000 claims description 12
- 239000010949 copper Substances 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910000679 solder Inorganic materials 0.000 claims description 8
- 239000000696 magnetic material Substances 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010453 quartz Substances 0.000 claims description 6
- 239000000654 additive Substances 0.000 claims description 4
- ZGWQKLYPIPNASE-UHFFFAOYSA-N [Co].[Zr].[Ta] Chemical compound [Co].[Zr].[Ta] ZGWQKLYPIPNASE-UHFFFAOYSA-N 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 239000002184 metal Substances 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000003990 capacitor Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000007726 management method Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910003321 CoFe Inorganic materials 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- KGWWEXORQXHJJQ-UHFFFAOYSA-N [Fe].[Co].[Ni] Chemical compound [Fe].[Co].[Ni] KGWWEXORQXHJJQ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- FQMNUIZEFUVPNU-UHFFFAOYSA-N cobalt iron Chemical compound [Fe].[Co].[Co] FQMNUIZEFUVPNU-UHFFFAOYSA-N 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- UGKDIUIOSMUOAW-UHFFFAOYSA-N iron nickel Chemical compound [Fe].[Ni] UGKDIUIOSMUOAW-UHFFFAOYSA-N 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/645—Inductive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13083—Three-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/13599—Material
- H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
- H01L2224/16267—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
- H01L2224/16268—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/19011—Structure including integrated passive components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
Definitions
- Various embodiments described herein relate to integrated circuit devices, and more particularly, to integrated circuit devices with voltage regulators.
- Voltage regulators have been implemented in conventional dedicated power management integrated circuits (PMICs).
- PMICs dedicated power management integrated circuits
- a conventional PMIC which is separate from other integrated circuits on a circuit board, may have difficulty meeting the droop (transient) and power (efficiency) requirements of a modem multi-core application processor or communication processor, for example.
- Integrated voltage regulators may present several challenges in chip design and layout.
- passive components such as inductors and capacitors in voltage regulators may pose a design challenge, because passive components, such as inductors and capacitors, especially those with large inductance and capacitance values, typically have large form factors requiring large surface areas in a typical layout for a silicon SOC die.
- inductors in voltage regulators typically require very low resistances to minimize power losses in voltage regulation.
- inductors may require thick metal traces on the SOC die in order to reduce the resistance values of the inductors.
- thick metal traces may not be feasible.
- conventional fabrication processes for integrating inductors as part of a voltage regulator on a silicon SOC die may require several additional masks, thereby increasing the cost of fabrication.
- Exemplary embodiments of the disclosure are directed to integrated circuit devices and methods of making the same.
- a voltage regulator is integrated or embedded in a system-on-chip (SOC) device which also includes one or more circuits using the voltage supplied by the voltage regulator.
- SOC system-on-chip
- a device comprising: a system-on-chip (SOC) wafer; an inductor wafer having first and second surfaces and a plurality of vias therethrough, the vias forming a plurality of sidewalls in the inductor wafer, wherein the first surface of the inductor wafer is disposed adjacent to the SOC wafer; a magnetic layer on at least a portion of the first surface of the inductor wafer; and a conductive layer disposed on the magnetic layer, on at least a portion of the second surface of the inductor wafer, and on at least some of the sidewalls formed by the vias in the inductor wafer.
- SOC system-on-chip
- a device comprising: a voltage regulator, comprising: a die; an inductor wafer having first and second surfaces and a plurality of vias therethrough, the vias forming a plurality of sidewalls in the inductor wafer, wherein the first surface of the inductor wafer is disposed adjacent to the die; a magnetic layer on at least a portion of the first surface of the inductor wafer; and a plurality of conductors disposed within at least some of the vias in the inductor wafer, the conductors having respective first ends adjacent to the first surface of the inductor wafer and second ends adjacent to the second surface of the inductor wafer; and a system-on-chip (SOC) package configured to receive a power supply voltage from the voltage regulator, the SOC package having at least one conductor connected to at least one of the first and second ends of the conductors.
- SOC system-on-chip
- a method of making a device comprising: providing a first wafer having a first surface and a second surface; forming a plurality of vias through the first and second surfaces of the first wafer, wherein the vias are defined by a plurality of sidewalls within the first wafer; forming a patterned magnetic layer on at least a portion of the first surface of the first wafer; forming a conductive layer on the patterned magnetic layer over the patterned magnetic layer, at least a portion of the second surface of the first wafer, and at least some of the sidewalls of the vias; and joining a second wafer to the first wafer.
- a method of making a device comprising: providing a system-on-chip (SOC) package; and forming a voltage regulator on the SOC package, comprising: providing an SOC die; providing an inductor wafer having first and second surfaces, wherein the first surface of the inductor wafer is disposed adjacent to the SOC die; forming a plurality of vias through the first and second surfaces of the inductor wafer, wherein the vias are defined by a plurality of sidewalls in the inductor wafer; and forming a plurality of conductors disposed within at least some of the vias in the inductor wafer, the conductors having respective first ends adjacent to the first surface of the inductor wafer and second ends adjacent to the second surface of the inductor wafer, wherein the SOC package is configured to receive a power supply voltage from the voltage regulator, the SOC package having at least one conductor connected to at least one of the first and second ends of the conductors.
- SOC system-on-chip
- FIG. 1 is a perspective view illustrating an embodiment of a system-on-chip (SOC) wafer.
- SOC system-on-chip
- FIG. 2 is a perspective view illustrating an embodiment of an inductor wafer with through vias.
- FIG. 3 is a perspective view illustrating an embodiment of face-to-face wafer-to-wafer bonding of an SOC wafer and an inductor wafer.
- FIG. 4 is a sectional view illustrating an embodiment of a first process step in the manufacturing of an inductor on an inductor wafer with through vias.
- FIG. 5 is a sectional view illustrating an embodiment of a second process step in the manufacturing of the inductor with a patterned thin-film magnetic layer.
- FIG. 6 is a sectional view of an embodiment of a third process step in the manufacturing of the inductor with a dielectric on the thin-film magnetic layer.
- FIG. 7 is a sectional view of an embodiment of a fourth process step in the manufacturing of the inductor with metal plating.
- FIG. 8 is a top plan view of an inductor having a coil with multiple loops.
- FIG. 9 is a sectional view illustrating an embodiment of a fifth process step in the manufacturing of a system-on-chip (SOC) device by joining an SOC wafer with an inductor wafer.
- SOC system-on-chip
- FIG. 10 is a sectional view illustrating an embodiment of the SOC device of FIG. 9 after the SOC wafer and the inductor wafer are joined together.
- FIG. 11 is a perspective view illustrating an embodiment of an inductor die after dicing of the joined SOC wafer and inductor wafer.
- FIG. 12 is a sectional view illustrating an embodiment of a system including a printed circuit board (PCB), an SOC package, and a voltage regulator which includes an inductor die.
- PCB printed circuit board
- SOC package SOC package
- voltage regulator which includes an inductor die.
- FIG. 13 is a diagram illustrating am embodiment of a system including a power management integrated circuit (PMIC) and an SOC device which includes an integrated or embedded voltage regulator and circuit using the voltage regulator.
- PMIC power management integrated circuit
- FIG. 1 is a perspective view illustrating an embodiment of a system-on-chip (SOC) wafer 100 having a first surface 102 and a second surface 104 opposite each other.
- the SOC wafer 100 comprises a semiconductor wafer, such as a silicon wafer.
- the SOC wafer 100 may comprise a glass wafer, a quartz wafer, an organic wafer, or a wafer made of another material.
- the SOC wafer 100 may be integrated with an inductor wafer on which one or more inductors are provided.
- FIG. 2 is a perspective view illustrating an embodiment of an inductor wafer 200 with a plurality of through vias 202 a , 202 b , 202 c , . . . .
- the inductor wafer 200 has first and second surfaces 204 and 206 opposite each other, and the vias 202 a , 202 b , 202 c , . . . are formed through the first and second surfaces 204 and 206 of the inductor wafer 200 .
- the inductor wafer 200 comprises a glass wafer.
- the inductor wafer 200 may comprise a quartz wafer, an organic wafer, or another type of low-loss dielectric material, to ensure that the inductor fabricated on the inductor wafer 200 has a low parasitic loss.
- the inductor wafer 200 may comprise a quartz wafer, an organic wafer, or another type of low-loss dielectric material, to ensure that the inductor fabricated on the inductor wafer 200 has a low parasitic loss.
- detailed structure of the conductors in the vias 202 a , 202 b , 202 c , . . . and the patterned conductive layers on the first and second surfaces 204 and 206 of the inductor wafer 200 which form one or more coils of an integrated inductor are not shown in the perspective view of FIG. 2 .
- Embodiments of the integrated inductor formed on the inductor wafer 200 will be described in further detail below with respect to FIGS. 4-7 and the top plan view of FIG. 8 .
- FIG. 3 is a perspective view illustrating an embodiment of face-to-face wafer-to-wafer bonding of the SOC wafer 100 and the inductor wafer 200 .
- the second surface 104 of the SOC wafer 100 is joined with the first surface 204 of the inductor wafer 200 .
- detailed structure of the integrated inductor formed on the inductor wafer 200 is omitted in FIG. 3 for simplicity of illustration. Embodiments of the integrated inductor formed on the inductor wafer 200 will be described with respect to FIGS. 4-8 .
- FIG. 4 is a sectional view illustrating an embodiment of a first process step in the manufacturing of an inductor on an inductor wafer with through vias.
- an inductor wafer 400 having a first surface 402 and a second surface 404 is provided.
- the inductor wafer 400 may be a glass wafer, a quartz wafer, or another type of wafer made of a low-loss dielectric material, for example.
- first and second vias 406 and 408 are formed within the inductor wafer 400 through the first and second surfaces 402 and 404 .
- FIG. 5 is a sectional view illustrating an embodiment of a second process step in the manufacturing of the inductor with a magnetic layer.
- a magnetic layer such as a patterned thin-film magnetic layer 410 , is formed on the first surface 402 of the inductor wafer 400 .
- the patterned thin-film magnetic layer 410 is formed on the first surface 402 of the portion of the inductor wafer 400 between the first and second vias 406 and 408 .
- the patterned thin-film magnetic layer 410 may be fabricated in various manners.
- a magnetic material such as cobalt-tantalum-zirconium (CoTaZr)
- CoTaZr cobalt-tantalum-zirconium
- Other magnetic materials such as alloys of nickel-iron (NiFe), cobalt-iron (CoFe), or cobalt-nickel-iron (CoNiFe), with added materials such as phosphorus (P), boron (B) or carbon (C), may be used for the patterned thin-film magnetic layer 410 to tailor the magnetic and electrical properties of the patterned thin-film magnetic layer 410 .
- the magnetic material for the patterned thin-film magnetic layer 410 is chosen so as to enable a boost in the inductance value of the inductor at the appropriate operating frequencies.
- Other types of magnetic materials may also be implemented as the patterned thin-film magnetic layer 410 .
- the magnetic layer 410 may also be formed by other techniques, for example, by sputtering a magnetic material on the first surface 402 of the inductor wafer 400 .
- FIG. 6 is a sectional view of an embodiment of a third process step in the manufacturing of the inductor with a dielectric on the patterned thin-film magnetic layer.
- a dielectric layer 412 is formed on top of the patterned thin-film magnetic layer 410 .
- the dielectric layer 412 covers the entire top and side surfaces of the thin-film magnetic layer 410 , as well as portions of the first surface 402 of the inductor wafer 400 surrounding the patterned thin-film magnetic layer 410 .
- the dielectric layer 412 comprises a polymer dielectric material.
- the dielectric layer 412 comprises an inorganic dielectric material, for example, silicon dioxide (SiO 2 ). Other types of dielectric materials may also be used for the dielectric layer 412 within the scope of the disclosure.
- FIG. 7 is a sectional view of an embodiment of a fourth process step in the manufacturing of the inductor with metal plating.
- the first via 406 has sidewalls 414 and 416
- the second via 408 has sidewalls 418 and 420 between the first and second surfaces 402 and 404 of the inductor wafer 400 .
- a conductive layer 422 is formed on the dielectric layer 412 , on the sidewall 416 of the first via 406 , on the sidewall 418 of the second via 408 , and on the second surface 404 of the inductor wafer 400 between the first and second vias 406 and 408 .
- the conductive layer 422 is formed by metal plating.
- the conductive layer is formed by semi-additive plating of a metal such as copper (Cu).
- a metal such as copper (Cu).
- the sidewall 414 opposite the sidewall 416 the first via 406 and at least portions of the first and second surfaces 402 and 404 of the inductor wafer 400 adjacent to the sidewall 414 are also covered by a conductive layer 424 .
- the sidewall 420 opposite the sidewall 418 the second via 408 and at least portions of the first and second surfaces 402 and 404 of the inductor wafer 400 adjacent to the sidewall 420 are also covered by a conductive layer 426 .
- the conductive layers 424 and 426 may also be formed by metal plating, such as semi-additive copper plating.
- the conductive layer 422 is shown as a section of one loop of an inductor coil which comprises a plurality of loops.
- a top plan view of an embodiment of a solenoid inductor which comprises an inductor coil with multiple loops is shown in FIG. 8 , which will be described in further detail below.
- Other inductor topologies for example, spiral inductors, toroid inductors, or racetrack inductors, may also be implemented instead of the solenoid inductor in the embodiments described and illustrated herein.
- a solenoid inductor may be chosen for its small footprint and easy, efficient integration closest to the circuitry on the SOC die.
- the conductive layer 422 which is illustrated as the sectional view of one loop of coil of an inductor, surrounds the thin-film magnetic layer 410 , which is implemented as a magnetic core of the inductor.
- another magnetic layer may be provided within the inductor coil, for example, a magnetic layer formed on the second surface 404 of the inductor wafer 400 opposite the magnetic layer 410 as shown in FIG. 7 , to increase the overall magnetic flux and thus the overall inductance of the inductor.
- an inductor with multiple loops of coil, with each loop having a sectional view similar to the sectional view of the conductive layer 422 as shown in FIG. 7 may be provided without any magnetic layer inside the coil, although such an inductor with no magnetic core would have a lower inductance compared to an inductor of the same size and the same number of loops having one or more magnetic cores.
- FIG. 8 is a top plan view of an inductor 800 having a coil 802 with multiple loops before the SOC wafer is joined with the inductor wafer.
- a sectional view of one of the loops 804 taken along sectional line 806 a - 806 b is illustrated in FIG. 7 .
- the inductor 800 has two terminals 808 and 810 at two opposite ends of the coil 802 for electrical connections with other circuit components in a voltage regulator, for example.
- some of the pass-through vias in the inductor wafer 400 like the first via 406 and the second via 408 as illustrated in FIGS.
- the conductive layer 422 which may comprise a thick Cu plating on the inductor wafer 200 , can be used as an additional routing layer to improve the performance of an advanced node SOC device with an advanced node SOC wafer 100 .
- the thick Cu plating of the conductive layer 422 can be used to reduce the number of Cu layers in the advanced node SOC wafer 100 , or in the package substrate 1212 , or both.
- FIG. 9 is a sectional view illustrating an embodiment of a fifth process step in the manufacturing of a system-on-chip (SOC) device by joining an SOC wafer with an inductor wafer.
- the SOC wafer 100 is provided with a plurality of metal columns, such as metal column 902 on the second surface 104 of the SOC wafer.
- a solder 904 is provided on the metal column 902 for joining with a respective metal-plated via of the inductor wafer.
- the metal column 902 on the second surface 104 of the SOC wafer 100 is aligned with the via 408 in the inductor wafer 400 , which is described above with respect to FIG. 7 .
- the thin-film magnetic layer 410 and the dielectric layer 412 are omitted in the sectional view of FIG. 9 .
- FIG. 10 is a sectional view illustrating an embodiment of the SOC device of FIG. 9 after the SOC wafer and the inductor wafer are joined together.
- the solder 904 connects the top portions of conductors 422 and 426 over the sidewalls 418 and 420 of the via 408 , respectively, and is positioned directly over the via 408 in the inductor wafer 400 .
- the solder 904 may comprise a conventional solder material that melts under heat and solidifies when the temperature cools down.
- FIG. 11 is a perspective view illustrating an embodiment of an inductor die after dicing of the joined SOC wafer and inductor wafer.
- multiple identical chips may be fabricated on a single wafer with a large surface area.
- a chip may be separated from a wafer by one of many dicing techniques known to persons skilled in the art.
- the joined SOC wafer 100 and the inductor wafer 200 may be diced into a plurality of dies 1102 a , 1102 b , 1102 c , . . . .
- Any one of the dies 1102 a , 1102 b , 1102 c , . . . may include one or more inductors and one or more other components, such as one or more capacitors, as part of an integrated or embedded voltage regulator.
- FIG. 12 is a sectional view illustrating an embodiment of a system including a printed circuit board (PCB), an SOC package, and a voltage regulator which includes an inductor die.
- a printed circuit board (PCB) 1202 is provided, and an IC package 1204 is provided on the PCB 1202 .
- the IC package may include one or more analog integrated circuits, one or more digital integrated circuits, or a combination thereof.
- the IC package 1204 may have one of various configurations known to persons skilled in the art, including but not limited to wirebond, flip-chip, or ball grid array (BGA), for example.
- BGA ball grid array
- a die 1206 that includes an inductor fabricated on an inductor wafer with through vias and joined with an SOC wafer in embodiments described above with respect to FIGS. 1-11 is integrated with the IC package 1204 .
- the IC package 1204 includes a package substrate 1212 .
- the die 1206 may be provided as a part of the circuitry for an integrated or embedded voltage regulator 1208 , which may also include other components.
- the voltage regulator 1208 may include one or more additional passive components such as one or more capacitors.
- the rest of the circuitry for the voltage regulator 1208 are generically indicated by block 1210 .
- FIG. 13 is a simplified block diagram illustrating am embodiment of a system including a power management integrated circuit (PMIC) and an SOC device which includes an integrated or embedded voltage regulator and circuit using the voltage regulator.
- the PMIC 1302 is shown as a chip separate from the SOC device 1304 . In an alternate embodiment, the PMIC 1302 may be integrated as part of the SOC device 1304 .
- the SOC device includes an inductor and capacitor (L & C) block 1306 , a voltage regulator (VR) 1308 , and one or more circuits 1310 using the output voltage from the VR 1308 .
- the inductor and capacitor in the L & C block 1306 may be integrated or embedded with the VR 1308 on the same chip as the circuits 1310 using the output voltage from the VR 1308 in an SOC device.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
Abstract
Description
- Various embodiments described herein relate to integrated circuit devices, and more particularly, to integrated circuit devices with voltage regulators.
- Voltage regulators have been implemented in conventional dedicated power management integrated circuits (PMICs). A conventional PMIC, which is separate from other integrated circuits on a circuit board, may have difficulty meeting the droop (transient) and power (efficiency) requirements of a modem multi-core application processor or communication processor, for example.
- There has been a growing interest in integrating voltage regulators as part of system-on-chip (SOC) integrated circuit devices. Integrated voltage regulators, however, may present several challenges in chip design and layout. For example, passive components such as inductors and capacitors in voltage regulators may pose a design challenge, because passive components, such as inductors and capacitors, especially those with large inductance and capacitance values, typically have large form factors requiring large surface areas in a typical layout for a silicon SOC die.
- Moreover, inductors in voltage regulators typically require very low resistances to minimize power losses in voltage regulation. In addition to occupying a significant amount of surface area of a typical silicon SOC die, such inductors may require thick metal traces on the SOC die in order to reduce the resistance values of the inductors. In advanced-node SOC wafer fabrication, however, such thick metal traces may not be feasible. Moreover, even if thick metal traces are implementable on a silicon SOC die, conventional fabrication processes for integrating inductors as part of a voltage regulator on a silicon SOC die may require several additional masks, thereby increasing the cost of fabrication.
- Exemplary embodiments of the disclosure are directed to integrated circuit devices and methods of making the same. In an embodiment, a voltage regulator is integrated or embedded in a system-on-chip (SOC) device which also includes one or more circuits using the voltage supplied by the voltage regulator.
- In an embodiment, a device is provided, the device comprising: a system-on-chip (SOC) wafer; an inductor wafer having first and second surfaces and a plurality of vias therethrough, the vias forming a plurality of sidewalls in the inductor wafer, wherein the first surface of the inductor wafer is disposed adjacent to the SOC wafer; a magnetic layer on at least a portion of the first surface of the inductor wafer; and a conductive layer disposed on the magnetic layer, on at least a portion of the second surface of the inductor wafer, and on at least some of the sidewalls formed by the vias in the inductor wafer.
- In another embodiment, a device is provided, the device comprising: a voltage regulator, comprising: a die; an inductor wafer having first and second surfaces and a plurality of vias therethrough, the vias forming a plurality of sidewalls in the inductor wafer, wherein the first surface of the inductor wafer is disposed adjacent to the die; a magnetic layer on at least a portion of the first surface of the inductor wafer; and a plurality of conductors disposed within at least some of the vias in the inductor wafer, the conductors having respective first ends adjacent to the first surface of the inductor wafer and second ends adjacent to the second surface of the inductor wafer; and a system-on-chip (SOC) package configured to receive a power supply voltage from the voltage regulator, the SOC package having at least one conductor connected to at least one of the first and second ends of the conductors.
- In another embodiment, a method of making a device is provided, the method comprising: providing a first wafer having a first surface and a second surface; forming a plurality of vias through the first and second surfaces of the first wafer, wherein the vias are defined by a plurality of sidewalls within the first wafer; forming a patterned magnetic layer on at least a portion of the first surface of the first wafer; forming a conductive layer on the patterned magnetic layer over the patterned magnetic layer, at least a portion of the second surface of the first wafer, and at least some of the sidewalls of the vias; and joining a second wafer to the first wafer.
- In yet another embodiment, a method of making a device is provided, the method comprising: providing a system-on-chip (SOC) package; and forming a voltage regulator on the SOC package, comprising: providing an SOC die; providing an inductor wafer having first and second surfaces, wherein the first surface of the inductor wafer is disposed adjacent to the SOC die; forming a plurality of vias through the first and second surfaces of the inductor wafer, wherein the vias are defined by a plurality of sidewalls in the inductor wafer; and forming a plurality of conductors disposed within at least some of the vias in the inductor wafer, the conductors having respective first ends adjacent to the first surface of the inductor wafer and second ends adjacent to the second surface of the inductor wafer, wherein the SOC package is configured to receive a power supply voltage from the voltage regulator, the SOC package having at least one conductor connected to at least one of the first and second ends of the conductors.
- The accompanying drawings are presented to aid in the description of embodiments of the disclosure and are provided solely for illustration of the embodiments and not limitation thereof.
-
FIG. 1 is a perspective view illustrating an embodiment of a system-on-chip (SOC) wafer. -
FIG. 2 is a perspective view illustrating an embodiment of an inductor wafer with through vias. -
FIG. 3 is a perspective view illustrating an embodiment of face-to-face wafer-to-wafer bonding of an SOC wafer and an inductor wafer. -
FIG. 4 is a sectional view illustrating an embodiment of a first process step in the manufacturing of an inductor on an inductor wafer with through vias. -
FIG. 5 is a sectional view illustrating an embodiment of a second process step in the manufacturing of the inductor with a patterned thin-film magnetic layer. -
FIG. 6 is a sectional view of an embodiment of a third process step in the manufacturing of the inductor with a dielectric on the thin-film magnetic layer. -
FIG. 7 is a sectional view of an embodiment of a fourth process step in the manufacturing of the inductor with metal plating. -
FIG. 8 is a top plan view of an inductor having a coil with multiple loops. -
FIG. 9 is a sectional view illustrating an embodiment of a fifth process step in the manufacturing of a system-on-chip (SOC) device by joining an SOC wafer with an inductor wafer. -
FIG. 10 is a sectional view illustrating an embodiment of the SOC device ofFIG. 9 after the SOC wafer and the inductor wafer are joined together. -
FIG. 11 is a perspective view illustrating an embodiment of an inductor die after dicing of the joined SOC wafer and inductor wafer. -
FIG. 12 is a sectional view illustrating an embodiment of a system including a printed circuit board (PCB), an SOC package, and a voltage regulator which includes an inductor die. -
FIG. 13 is a diagram illustrating am embodiment of a system including a power management integrated circuit (PMIC) and an SOC device which includes an integrated or embedded voltage regulator and circuit using the voltage regulator. - Aspects of the disclosure are described in the following description and related drawings directed to specific embodiments. Alternate embodiments may be devised without departing from the scope of the disclosure. Additionally, well-known elements will not be described in detail or will be omitted so as not to obscure the relevant details of the disclosure.
- The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term “embodiments” does not require that all embodiments include the discussed feature, advantage or mode of operation.
- The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Moreover, it is understood that the word “or” has the same meaning as the Boolean operator “OR,” that is, it encompasses the possibilities of “either” and “both” and is not limited to “exclusive or” (“XOR”), unless expressly stated otherwise. It is also understood that the symbol “I” between two adjacent words has the same meaning as “or” unless expressly stated otherwise. Moreover, phrases such as “connected to,” “coupled to” or “in communication with” are not limited to direct connections unless expressly stated otherwise.
-
FIG. 1 is a perspective view illustrating an embodiment of a system-on-chip (SOC) wafer 100 having afirst surface 102 and asecond surface 104 opposite each other. In an embodiment, theSOC wafer 100 comprises a semiconductor wafer, such as a silicon wafer. In alternate embodiments, theSOC wafer 100 may comprise a glass wafer, a quartz wafer, an organic wafer, or a wafer made of another material. In an embodiment, theSOC wafer 100 may be integrated with an inductor wafer on which one or more inductors are provided. -
FIG. 2 is a perspective view illustrating an embodiment of aninductor wafer 200 with a plurality of throughvias FIG. 2 , theinductor wafer 200 has first andsecond surfaces vias second surfaces inductor wafer 200. In an embodiment, theinductor wafer 200 comprises a glass wafer. In alternate embodiments, theinductor wafer 200 may comprise a quartz wafer, an organic wafer, or another type of low-loss dielectric material, to ensure that the inductor fabricated on theinductor wafer 200 has a low parasitic loss. For simplicity of illustration, detailed structure of the conductors in thevias second surfaces inductor wafer 200 which form one or more coils of an integrated inductor are not shown in the perspective view ofFIG. 2 . Embodiments of the integrated inductor formed on theinductor wafer 200 will be described in further detail below with respect toFIGS. 4-7 and the top plan view ofFIG. 8 . -
FIG. 3 is a perspective view illustrating an embodiment of face-to-face wafer-to-wafer bonding of theSOC wafer 100 and theinductor wafer 200. In this embodiment, thesecond surface 104 of theSOC wafer 100 is joined with thefirst surface 204 of theinductor wafer 200. Again, detailed structure of the integrated inductor formed on theinductor wafer 200 is omitted inFIG. 3 for simplicity of illustration. Embodiments of the integrated inductor formed on theinductor wafer 200 will be described with respect toFIGS. 4-8 . -
FIG. 4 is a sectional view illustrating an embodiment of a first process step in the manufacturing of an inductor on an inductor wafer with through vias. InFIG. 4 , an inductor wafer 400 having afirst surface 402 and asecond surface 404 is provided. Theinductor wafer 400 may be a glass wafer, a quartz wafer, or another type of wafer made of a low-loss dielectric material, for example. In the embodiment shown inFIG. 4 , first andsecond vias second surfaces -
FIG. 5 is a sectional view illustrating an embodiment of a second process step in the manufacturing of the inductor with a magnetic layer. InFIG. 5 , a magnetic layer, such as a patterned thin-filmmagnetic layer 410, is formed on thefirst surface 402 of theinductor wafer 400. In the embodiment illustrated inFIG. 5 , the patterned thin-filmmagnetic layer 410 is formed on thefirst surface 402 of the portion of theinductor wafer 400 between the first andsecond vias - The patterned thin-film
magnetic layer 410 may be fabricated in various manners. For example, a magnetic material, such as cobalt-tantalum-zirconium (CoTaZr), may be deposited by vacuum processes, plated, screen-printed, or laminated onto thefirst surface 402 of theinductor wafer 400 to form the thin-filmmagnetic layer 410. Other magnetic materials, such as alloys of nickel-iron (NiFe), cobalt-iron (CoFe), or cobalt-nickel-iron (CoNiFe), with added materials such as phosphorus (P), boron (B) or carbon (C), may be used for the patterned thin-filmmagnetic layer 410 to tailor the magnetic and electrical properties of the patterned thin-filmmagnetic layer 410. In an embodiment, the magnetic material for the patterned thin-filmmagnetic layer 410 is chosen so as to enable a boost in the inductance value of the inductor at the appropriate operating frequencies. Other types of magnetic materials may also be implemented as the patterned thin-filmmagnetic layer 410. Themagnetic layer 410 may also be formed by other techniques, for example, by sputtering a magnetic material on thefirst surface 402 of theinductor wafer 400. -
FIG. 6 is a sectional view of an embodiment of a third process step in the manufacturing of the inductor with a dielectric on the patterned thin-film magnetic layer. InFIG. 6 , adielectric layer 412 is formed on top of the patterned thin-filmmagnetic layer 410. In the embodiment illustrated inFIG. 6 , thedielectric layer 412 covers the entire top and side surfaces of the thin-filmmagnetic layer 410, as well as portions of thefirst surface 402 of theinductor wafer 400 surrounding the patterned thin-filmmagnetic layer 410. In an embodiment, thedielectric layer 412 comprises a polymer dielectric material. In an alternate embodiment, thedielectric layer 412 comprises an inorganic dielectric material, for example, silicon dioxide (SiO2). Other types of dielectric materials may also be used for thedielectric layer 412 within the scope of the disclosure. -
FIG. 7 is a sectional view of an embodiment of a fourth process step in the manufacturing of the inductor with metal plating. In the sectional view shown inFIG. 7 , the first via 406 has sidewalls 414 and 416, and likewise, the second via 408 has sidewalls 418 and 420 between the first andsecond surfaces inductor wafer 400. In an embodiment, aconductive layer 422 is formed on thedielectric layer 412, on thesidewall 416 of the first via 406, on thesidewall 418 of the second via 408, and on thesecond surface 404 of theinductor wafer 400 between the first andsecond vias conductive layer 422 is formed by metal plating. - In a further embodiment, the conductive layer is formed by semi-additive plating of a metal such as copper (Cu). In the sectional view shown in
FIG. 7 , thesidewall 414 opposite thesidewall 416 the first via 406 and at least portions of the first andsecond surfaces inductor wafer 400 adjacent to thesidewall 414 are also covered by aconductive layer 424. Likewise, as shown inFIG. 7 , thesidewall 420 opposite thesidewall 418 the second via 408 and at least portions of the first andsecond surfaces inductor wafer 400 adjacent to thesidewall 420 are also covered by aconductive layer 426. Similar to theconductive layer 422, theconductive layers - In the embodiment illustrated in the sectional view of
FIG. 7 , theconductive layer 422 is shown as a section of one loop of an inductor coil which comprises a plurality of loops. A top plan view of an embodiment of a solenoid inductor which comprises an inductor coil with multiple loops is shown inFIG. 8 , which will be described in further detail below. Other inductor topologies, for example, spiral inductors, toroid inductors, or racetrack inductors, may also be implemented instead of the solenoid inductor in the embodiments described and illustrated herein. In an SOC package with a limited amount of space, however, a solenoid inductor may be chosen for its small footprint and easy, efficient integration closest to the circuitry on the SOC die. - Referring to the embodiment shown in
FIG. 7 , theconductive layer 422, which is illustrated as the sectional view of one loop of coil of an inductor, surrounds the thin-filmmagnetic layer 410, which is implemented as a magnetic core of the inductor. In an alternate embodiment, another magnetic layer may be provided within the inductor coil, for example, a magnetic layer formed on thesecond surface 404 of theinductor wafer 400 opposite themagnetic layer 410 as shown inFIG. 7 , to increase the overall magnetic flux and thus the overall inductance of the inductor. In another alternate embodiment, an inductor with multiple loops of coil, with each loop having a sectional view similar to the sectional view of theconductive layer 422 as shown inFIG. 7 , may be provided without any magnetic layer inside the coil, although such an inductor with no magnetic core would have a lower inductance compared to an inductor of the same size and the same number of loops having one or more magnetic cores. -
FIG. 8 is a top plan view of aninductor 800 having acoil 802 with multiple loops before the SOC wafer is joined with the inductor wafer. In an embodiment, a sectional view of one of theloops 804 taken along sectional line 806 a-806 b is illustrated inFIG. 7 . Referring to the top plan view ofFIG. 8 , theinductor 800 has twoterminals coil 802 for electrical connections with other circuit components in a voltage regulator, for example. In an embodiment, some of the pass-through vias in theinductor wafer 400, like the first via 406 and the second via 408 as illustrated inFIGS. 4-7 , may be used to form electrical connections between die pads on the SOC die and pads on the substrate. For example, some of the pass-through vias may be connected to enable power supply connections and/or to provide ground planes to improve power delivery to the SOC die. In an embodiment, theconductive layer 422, which may comprise a thick Cu plating on theinductor wafer 200, can be used as an additional routing layer to improve the performance of an advanced node SOC device with an advancednode SOC wafer 100. In a further embodiment, by using a combined design of the advancednode SOC wafer 100, theinductor wafer 200, and apackage substrate 1212 on an integrated circuit (IC)package 1204, which will be described in further detail below with respect toFIG. 12 , the thick Cu plating of theconductive layer 422 can be used to reduce the number of Cu layers in the advancednode SOC wafer 100, or in thepackage substrate 1212, or both. -
FIG. 9 is a sectional view illustrating an embodiment of a fifth process step in the manufacturing of a system-on-chip (SOC) device by joining an SOC wafer with an inductor wafer. In an embodiment, theSOC wafer 100 is provided with a plurality of metal columns, such asmetal column 902 on thesecond surface 104 of the SOC wafer. In an embodiment, asolder 904 is provided on themetal column 902 for joining with a respective metal-plated via of the inductor wafer. In the sectional view illustrated inFIG. 9 , themetal column 902 on thesecond surface 104 of theSOC wafer 100 is aligned with the via 408 in theinductor wafer 400, which is described above with respect toFIG. 7 . For simplicity of illustration, the thin-filmmagnetic layer 410 and thedielectric layer 412 are omitted in the sectional view ofFIG. 9 . -
FIG. 10 is a sectional view illustrating an embodiment of the SOC device ofFIG. 9 after the SOC wafer and the inductor wafer are joined together. In the embodiment illustrated inFIG. 10 , thesolder 904 connects the top portions ofconductors sidewalls inductor wafer 400. In an embodiment, thesolder 904 may comprise a conventional solder material that melts under heat and solidifies when the temperature cools down. -
FIG. 11 is a perspective view illustrating an embodiment of an inductor die after dicing of the joined SOC wafer and inductor wafer. In typical wafer fabrication processes, multiple identical chips may be fabricated on a single wafer with a large surface area. In an embodiment, a chip may be separated from a wafer by one of many dicing techniques known to persons skilled in the art. In the embodiment shown inFIG. 11 , the joinedSOC wafer 100 and theinductor wafer 200 may be diced into a plurality of dies 1102 a, 1102 b, 1102 c, . . . . Any one of the dies 1102 a, 1102 b, 1102 c, . . . may include one or more inductors and one or more other components, such as one or more capacitors, as part of an integrated or embedded voltage regulator. -
FIG. 12 is a sectional view illustrating an embodiment of a system including a printed circuit board (PCB), an SOC package, and a voltage regulator which includes an inductor die. InFIG. 12 , a printed circuit board (PCB) 1202 is provided, and anIC package 1204 is provided on thePCB 1202. In an embodiment, the IC package may include one or more analog integrated circuits, one or more digital integrated circuits, or a combination thereof. In an embodiment, theIC package 1204 may have one of various configurations known to persons skilled in the art, including but not limited to wirebond, flip-chip, or ball grid array (BGA), for example. - Referring to
FIG. 12 , adie 1206 that includes an inductor fabricated on an inductor wafer with through vias and joined with an SOC wafer in embodiments described above with respect toFIGS. 1-11 is integrated with theIC package 1204. In an embodiment, theIC package 1204 includes apackage substrate 1212. In an embodiment, thedie 1206 may be provided as a part of the circuitry for an integrated or embeddedvoltage regulator 1208, which may also include other components. For example, thevoltage regulator 1208 may include one or more additional passive components such as one or more capacitors. InFIG. 12 , the rest of the circuitry for thevoltage regulator 1208 are generically indicated byblock 1210. -
FIG. 13 is a simplified block diagram illustrating am embodiment of a system including a power management integrated circuit (PMIC) and an SOC device which includes an integrated or embedded voltage regulator and circuit using the voltage regulator. In the embodiment illustrated inFIG. 13 , thePMIC 1302 is shown as a chip separate from theSOC device 1304. In an alternate embodiment, thePMIC 1302 may be integrated as part of theSOC device 1304. Referring toFIG. 13 , the SOC device includes an inductor and capacitor (L & C)block 1306, a voltage regulator (VR) 1308, and one ormore circuits 1310 using the output voltage from theVR 1308. In an embodiment, the inductor and capacitor in the L &C block 1306 may be integrated or embedded with theVR 1308 on the same chip as thecircuits 1310 using the output voltage from theVR 1308 in an SOC device. - While the foregoing disclosure shows illustrative embodiments, it should be noted that various changes and modifications could be made herein without departing from the scope of the appended claims. The functions, steps or actions of the method claims in accordance with embodiments described herein need not be performed in any particular order unless expressly stated otherwise. Furthermore, although elements may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
Claims (30)
Priority Applications (9)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/843,964 US20170062398A1 (en) | 2015-09-02 | 2015-09-02 | Integration of inductors with advanced-node system-on-chip (soc) using glass wafer with inductors and wafer-to-wafer joining |
EP16751137.7A EP3345218A1 (en) | 2015-09-02 | 2016-08-08 | Integration of inductors with advanced-node system-on-chip (soc) using glass wafer with inductors and wafer-to-wafer joining |
CN201680048793.1A CN108012565A (en) | 2015-09-02 | 2016-08-08 | It is using chip glass that inductor and advanced node system-on-chip (SOC) is integrated by inductor and wafer to wafer engagement |
JP2018509890A JP2018532260A (en) | 2015-09-02 | 2016-08-08 | Inductor integration and wafer-to-wafer bonding by advanced node system on chip (SOC) using glass wafer with inductor |
BR112018004288A BR112018004288A2 (en) | 2015-09-02 | 2016-08-08 | advanced node chip (soc) system inductor integration using inductor glass blade and blade to blade junction |
CA2992855A CA2992855A1 (en) | 2015-09-02 | 2016-08-08 | Integration of inductors with advanced-node system-on-chip (soc) using glass wafer with inductors and wafer-to-wafer joining |
KR1020187009210A KR102541387B1 (en) | 2015-09-02 | 2016-08-08 | Integration and wafer-to-wafer coupling of inductors with advanced-node SYSTEM-ON-CHIP (SOC) using a glass wafer with inductors |
PCT/US2016/045998 WO2017039962A1 (en) | 2015-09-02 | 2016-08-08 | Integration of inductors with advanced-node system-on-chip (soc) using glass wafer with inductors and wafer-to-wafer joining |
US17/408,273 US20210384292A1 (en) | 2015-09-02 | 2021-08-20 | Integration of inductors with advanced-node system-on-chip (soc) using glass wafer with inductors and wafer-to-wafer joining |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/843,964 US20170062398A1 (en) | 2015-09-02 | 2015-09-02 | Integration of inductors with advanced-node system-on-chip (soc) using glass wafer with inductors and wafer-to-wafer joining |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/408,273 Division US20210384292A1 (en) | 2015-09-02 | 2021-08-20 | Integration of inductors with advanced-node system-on-chip (soc) using glass wafer with inductors and wafer-to-wafer joining |
Publications (1)
Publication Number | Publication Date |
---|---|
US20170062398A1 true US20170062398A1 (en) | 2017-03-02 |
Family
ID=56684312
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/843,964 Abandoned US20170062398A1 (en) | 2015-09-02 | 2015-09-02 | Integration of inductors with advanced-node system-on-chip (soc) using glass wafer with inductors and wafer-to-wafer joining |
US17/408,273 Pending US20210384292A1 (en) | 2015-09-02 | 2021-08-20 | Integration of inductors with advanced-node system-on-chip (soc) using glass wafer with inductors and wafer-to-wafer joining |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/408,273 Pending US20210384292A1 (en) | 2015-09-02 | 2021-08-20 | Integration of inductors with advanced-node system-on-chip (soc) using glass wafer with inductors and wafer-to-wafer joining |
Country Status (8)
Country | Link |
---|---|
US (2) | US20170062398A1 (en) |
EP (1) | EP3345218A1 (en) |
JP (1) | JP2018532260A (en) |
KR (1) | KR102541387B1 (en) |
CN (1) | CN108012565A (en) |
BR (1) | BR112018004288A2 (en) |
CA (1) | CA2992855A1 (en) |
WO (1) | WO2017039962A1 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170169934A1 (en) * | 2015-12-15 | 2017-06-15 | Globalfoundries Inc. | Patterned magnetic shields for inductors and transformers |
WO2020005435A1 (en) * | 2018-06-29 | 2020-01-02 | Intel Corporation | Integrated magnetic core inductors on glass core substrates |
US20200203067A1 (en) * | 2017-09-29 | 2020-06-25 | Intel Corporation | Magnetic core/shell particles for inductor arrays |
US11450628B2 (en) * | 2019-12-15 | 2022-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure including a solenoid inductor laterally aside a die and method of fabricating the same |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9935076B1 (en) * | 2015-09-30 | 2018-04-03 | Apple Inc. | Structure and method for fabricating a computing system with an integrated voltage regulator module |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050105225A1 (en) * | 2003-08-06 | 2005-05-19 | Micron Technology, Inc. | Microtransformer for system-on-chip power supply |
US6976300B2 (en) * | 1999-07-09 | 2005-12-20 | Micron Technology, Inc. | Integrated circuit inductors |
US20140264734A1 (en) * | 2013-03-14 | 2014-09-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Inductor With Magnetic Material |
US20150137342A1 (en) * | 2013-11-20 | 2015-05-21 | Marvell World Trade Ltd. | Inductor/transformer outside of silicon wafer |
US20160254342A1 (en) * | 2015-02-26 | 2016-09-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Magnetic core, inductor, and method for fabricating the magnetic core |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060088971A1 (en) * | 2004-10-27 | 2006-04-27 | Crawford Ankur M | Integrated inductor and method of fabrication |
US7463131B1 (en) | 2005-01-24 | 2008-12-09 | National Semiconductor Corporation | Patterned magnetic layer on-chip inductor |
US9105627B2 (en) * | 2011-11-04 | 2015-08-11 | International Business Machines Corporation | Coil inductor for on-chip or on-chip stack |
-
2015
- 2015-09-02 US US14/843,964 patent/US20170062398A1/en not_active Abandoned
-
2016
- 2016-08-08 EP EP16751137.7A patent/EP3345218A1/en active Pending
- 2016-08-08 JP JP2018509890A patent/JP2018532260A/en active Pending
- 2016-08-08 BR BR112018004288A patent/BR112018004288A2/en not_active Application Discontinuation
- 2016-08-08 KR KR1020187009210A patent/KR102541387B1/en active IP Right Grant
- 2016-08-08 CN CN201680048793.1A patent/CN108012565A/en active Pending
- 2016-08-08 WO PCT/US2016/045998 patent/WO2017039962A1/en active Application Filing
- 2016-08-08 CA CA2992855A patent/CA2992855A1/en not_active Abandoned
-
2021
- 2021-08-20 US US17/408,273 patent/US20210384292A1/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6976300B2 (en) * | 1999-07-09 | 2005-12-20 | Micron Technology, Inc. | Integrated circuit inductors |
US20050105225A1 (en) * | 2003-08-06 | 2005-05-19 | Micron Technology, Inc. | Microtransformer for system-on-chip power supply |
US20140264734A1 (en) * | 2013-03-14 | 2014-09-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Inductor With Magnetic Material |
US20150137342A1 (en) * | 2013-11-20 | 2015-05-21 | Marvell World Trade Ltd. | Inductor/transformer outside of silicon wafer |
US20160254342A1 (en) * | 2015-02-26 | 2016-09-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Magnetic core, inductor, and method for fabricating the magnetic core |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170169934A1 (en) * | 2015-12-15 | 2017-06-15 | Globalfoundries Inc. | Patterned magnetic shields for inductors and transformers |
US20200203067A1 (en) * | 2017-09-29 | 2020-06-25 | Intel Corporation | Magnetic core/shell particles for inductor arrays |
WO2020005435A1 (en) * | 2018-06-29 | 2020-01-02 | Intel Corporation | Integrated magnetic core inductors on glass core substrates |
US11538617B2 (en) | 2018-06-29 | 2022-12-27 | Intel Corporation | Integrated magnetic core inductors on glass core substrates |
US11450628B2 (en) * | 2019-12-15 | 2022-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure including a solenoid inductor laterally aside a die and method of fabricating the same |
Also Published As
Publication number | Publication date |
---|---|
CN108012565A (en) | 2018-05-08 |
WO2017039962A1 (en) | 2017-03-09 |
US20210384292A1 (en) | 2021-12-09 |
KR20180048948A (en) | 2018-05-10 |
KR102541387B1 (en) | 2023-06-08 |
BR112018004288A2 (en) | 2018-10-09 |
EP3345218A1 (en) | 2018-07-11 |
JP2018532260A (en) | 2018-11-01 |
CA2992855A1 (en) | 2017-03-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20210384292A1 (en) | Integration of inductors with advanced-node system-on-chip (soc) using glass wafer with inductors and wafer-to-wafer joining | |
US9640604B2 (en) | Small size and fully integrated power converter with magnetics on chip | |
JP6285617B1 (en) | Integrated device package comprising a magnetic core inductor having a guard ring embedded in a package substrate | |
US20170309700A1 (en) | Integrated inductor for integrated circuit devices | |
US9153547B2 (en) | Integrated inductor structure and method of fabrication | |
TWI611437B (en) | Substrate-less discrete coupled inductor structure, inductor structure apparatus, and method for providing the inductor structure | |
CN107210231B (en) | Switched-mode power stage with integrated passive components | |
US9888577B2 (en) | Passive electrical devices with a polymer carrier | |
WO2011025897A1 (en) | Transformer signal coupling for flip-chip integration | |
US11723222B2 (en) | Integrated circuit (IC) package with integrated inductor having core magnetic field (B field) extending parallel to substrate | |
US11557420B2 (en) | Coupling inductors in an IC device using interconnecting elements with solder caps and resulting devices | |
US9006862B2 (en) | Electronic semiconductor device with integrated inductor, and manufacturing method | |
US10879169B2 (en) | Integrated inductors for power management circuits | |
US10470309B2 (en) | Inductor and capacitor integrated on a substrate | |
US20150137342A1 (en) | Inductor/transformer outside of silicon wafer | |
US20150311271A1 (en) | Landside embedded inductor for fanout packaging | |
TWI658567B (en) | Electronic package and its substrate structure | |
US20230082743A1 (en) | Integrated passive devices | |
TW202418311A (en) | Method for constructing solenoid inductor and solenoid inductor constructed by the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: QUALCOMM INCORPORATED, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ARABI, KARIM;SHENOY, RAVINDRA VAMAN;GOUSEV, EVGENI PETROVICH;AND OTHERS;REEL/FRAME:037073/0397 Effective date: 20151014 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |
|
STCV | Information on status: appeal procedure |
Free format text: NOTICE OF APPEAL FILED |
|
STCV | Information on status: appeal procedure |
Free format text: NOTICE OF APPEAL FILED |
|
STCV | Information on status: appeal procedure |
Free format text: APPEAL BRIEF (OR SUPPLEMENTAL BRIEF) ENTERED AND FORWARDED TO EXAMINER |
|
STCV | Information on status: appeal procedure |
Free format text: EXAMINER'S ANSWER TO APPEAL BRIEF MAILED |
|
STCV | Information on status: appeal procedure |
Free format text: ON APPEAL -- AWAITING DECISION BY THE BOARD OF APPEALS |
|
STCV | Information on status: appeal procedure |
Free format text: BOARD OF APPEALS DECISION RENDERED |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- AFTER EXAMINER'S ANSWER OR BOARD OF APPEALS DECISION |