BR112017008407A8 - Método de gerenciamento de sistema de cpu e múltiplas cpus - Google Patents
Método de gerenciamento de sistema de cpu e múltiplas cpusInfo
- Publication number
- BR112017008407A8 BR112017008407A8 BR112017008407A BR112017008407A BR112017008407A8 BR 112017008407 A8 BR112017008407 A8 BR 112017008407A8 BR 112017008407 A BR112017008407 A BR 112017008407A BR 112017008407 A BR112017008407 A BR 112017008407A BR 112017008407 A8 BR112017008407 A8 BR 112017008407A8
- Authority
- BR
- Brazil
- Prior art keywords
- cpu
- group
- management method
- system management
- ncs
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
- G06F15/8023—Two dimensional arrays, e.g. mesh, torus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
- G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
- G06F15/17343—Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
Abstract
A presente invenção fornece um sistema de múltiplas CPUs, em que o sistema de múltiplas CPUs inclui: pelo menos dois domínios de Interconexão de Caminho Rápido QPI, um primeiro grupo de NC de controlador de nó e um segundo grupo de NC de controlador de nó; de acordo com uma configuração de rota de CPU, há pelo menos uma CPU que pode acessar uma CPU em outro domínio de QPI com o uso do primeiro grupo de NC; e há pelo menos uma CPU que pode acessar uma CPU em outro domínio de QPI com o uso do segundo grupo de NC. De acordo com essa topologia, o hot swap de um NC pode ser implantado enquanto o sistema está levemente afetado.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2015/099589 WO2017113128A1 (zh) | 2015-12-29 | 2015-12-29 | 一种cpu及多cpu系统管理方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
BR112017008407A2 BR112017008407A2 (pt) | 2017-12-19 |
BR112017008407A8 true BR112017008407A8 (pt) | 2022-10-18 |
BR112017008407B1 BR112017008407B1 (pt) | 2023-04-04 |
Family
ID=57216272
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR112017008407-4A BR112017008407B1 (pt) | 2015-12-29 | 2015-12-29 | Método de gerenciamento de sistema de cpu e múltiplas cpus |
Country Status (12)
Country | Link |
---|---|
US (1) | US11138147B2 (pt) |
EP (2) | EP3575977A1 (pt) |
JP (1) | JP6536677B2 (pt) |
KR (1) | KR102092660B1 (pt) |
CN (2) | CN111427827B (pt) |
AU (1) | AU2015412144B2 (pt) |
BR (1) | BR112017008407B1 (pt) |
CA (1) | CA2965982C (pt) |
RU (1) | RU2658884C1 (pt) |
SG (1) | SG11201703261WA (pt) |
WO (1) | WO2017113128A1 (pt) |
ZA (1) | ZA201702790B (pt) |
Families Citing this family (9)
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CN105700975B (zh) * | 2016-01-08 | 2019-05-24 | 华为技术有限公司 | 一种中央处理器cpu热移除、热添加方法及装置 |
CN108701117B (zh) * | 2017-05-04 | 2022-03-29 | 华为技术有限公司 | 互连系统、互连控制方法和装置 |
JP7068681B2 (ja) * | 2017-06-02 | 2022-05-17 | 国立大学法人東京海洋大学 | 生殖細胞追跡用抗体 |
CN107396586A (zh) * | 2017-07-27 | 2017-11-24 | 郑州云海信息技术有限公司 | 一种减少背板层叠的upi互连系统 |
CN107526617B (zh) * | 2017-09-04 | 2020-12-29 | 井冈山电器有限公司 | 一种cpu更新方法及系统 |
CN108182163B (zh) * | 2018-01-02 | 2021-03-02 | 苏州浪潮智能科技有限公司 | 一种计算板级热插拔控制装置及控制方法 |
US11016822B1 (en) * | 2018-04-03 | 2021-05-25 | Xilinx, Inc. | Cascade streaming between data processing engines in an array |
CN112540941A (zh) * | 2019-09-21 | 2021-03-23 | 华为技术有限公司 | 一种数据转发芯片及服务器 |
CN114090095B (zh) * | 2022-01-19 | 2022-05-24 | 苏州浪潮智能科技有限公司 | 一种多路服务器中cpu的bios加载方法及相关组件 |
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US7477612B2 (en) * | 2002-03-15 | 2009-01-13 | Broadcom Corporation | Topology discovery process and mechanism for a network of managed devices |
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JP2007011580A (ja) * | 2005-06-29 | 2007-01-18 | Toshiba Corp | 情報処理装置 |
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US7761538B2 (en) * | 2006-08-30 | 2010-07-20 | Microsoft Corporation | Dynamically configuring, allocating and deploying computing systems |
US20090144476A1 (en) * | 2007-12-04 | 2009-06-04 | Xiaohua Cai | Hot plug in a link based system |
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JP5550089B2 (ja) * | 2009-03-30 | 2014-07-16 | エヌイーシーコンピュータテクノ株式会社 | マルチプロセッサシステム、ノードコントローラ、障害回復方式 |
US8224955B2 (en) * | 2009-05-07 | 2012-07-17 | International Business Machines Corporation | Ensuring affinity at all affinity domains by folding at each affinity level possible for a partition spanning multiple nodes |
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US20110161592A1 (en) * | 2009-12-31 | 2011-06-30 | Nachimuthu Murugasamy K | Dynamic system reconfiguration |
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US8677180B2 (en) * | 2010-06-23 | 2014-03-18 | International Business Machines Corporation | Switch failover control in a multiprocessor computer system |
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-
2015
- 2015-12-29 BR BR112017008407-4A patent/BR112017008407B1/pt active IP Right Grant
- 2015-12-29 CN CN202010104409.3A patent/CN111427827B/zh active Active
- 2015-12-29 EP EP19153258.9A patent/EP3575977A1/en active Pending
- 2015-12-29 EP EP15908486.2A patent/EP3226147B1/en active Active
- 2015-12-29 AU AU2015412144A patent/AU2015412144B2/en active Active
- 2015-12-29 CN CN201580012642.6A patent/CN106104505B/zh active Active
- 2015-12-29 RU RU2017119650A patent/RU2658884C1/ru active
- 2015-12-29 SG SG11201703261WA patent/SG11201703261WA/en unknown
- 2015-12-29 WO PCT/CN2015/099589 patent/WO2017113128A1/zh active Application Filing
- 2015-12-29 KR KR1020177012588A patent/KR102092660B1/ko active IP Right Grant
- 2015-12-29 CA CA2965982A patent/CA2965982C/en active Active
- 2015-12-29 JP JP2017529378A patent/JP6536677B2/ja active Active
-
2017
- 2017-04-20 ZA ZA2017/02790A patent/ZA201702790B/en unknown
- 2017-08-31 US US15/692,359 patent/US11138147B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
BR112017008407A2 (pt) | 2017-12-19 |
JP6536677B2 (ja) | 2019-07-03 |
EP3575977A1 (en) | 2019-12-04 |
AU2015412144B2 (en) | 2018-11-15 |
KR102092660B1 (ko) | 2020-03-24 |
SG11201703261WA (en) | 2017-08-30 |
EP3226147B1 (en) | 2019-12-04 |
ZA201702790B (en) | 2019-12-18 |
BR112017008407B1 (pt) | 2023-04-04 |
CA2965982C (en) | 2019-02-12 |
RU2658884C1 (ru) | 2018-06-25 |
JP2018507454A (ja) | 2018-03-15 |
CN106104505B (zh) | 2020-02-21 |
AU2015412144A1 (en) | 2017-07-13 |
US20170364475A1 (en) | 2017-12-21 |
EP3226147A1 (en) | 2017-10-04 |
CA2965982A1 (en) | 2017-06-29 |
CN111427827A (zh) | 2020-07-17 |
CN111427827B (zh) | 2023-03-17 |
EP3226147A4 (en) | 2017-12-27 |
WO2017113128A1 (zh) | 2017-07-06 |
KR20170093116A (ko) | 2017-08-14 |
US11138147B2 (en) | 2021-10-05 |
CN106104505A (zh) | 2016-11-09 |
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B06U | Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette] | ||
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Owner name: XFUSION DIGITAL TECHNOLOGIES CO., LTD. (CN) |
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