SG11201703261WA - Cpu and multi-cpu system management method - Google Patents

Cpu and multi-cpu system management method

Info

Publication number
SG11201703261WA
SG11201703261WA SG11201703261WA SG11201703261WA SG11201703261WA SG 11201703261W A SG11201703261W A SG 11201703261WA SG 11201703261W A SG11201703261W A SG 11201703261WA SG 11201703261W A SG11201703261W A SG 11201703261WA SG 11201703261W A SG11201703261W A SG 11201703261WA
Authority
SG
Singapore
Prior art keywords
cpu
management method
system management
cpu system
management
Prior art date
Application number
SG11201703261WA
Inventor
Gang Liu
Ben Chen
Liwei Cao
Original Assignee
Huawei Tech Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Tech Co Ltd filed Critical Huawei Tech Co Ltd
Publication of SG11201703261WA publication Critical patent/SG11201703261WA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • G06F15/17343—Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus
SG11201703261WA 2015-12-29 2015-12-29 Cpu and multi-cpu system management method SG11201703261WA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2015/099589 WO2017113128A1 (en) 2015-12-29 2015-12-29 Cpu, and method of managing multi-cpu system

Publications (1)

Publication Number Publication Date
SG11201703261WA true SG11201703261WA (en) 2017-08-30

Family

ID=57216272

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201703261WA SG11201703261WA (en) 2015-12-29 2015-12-29 Cpu and multi-cpu system management method

Country Status (12)

Country Link
US (1) US11138147B2 (en)
EP (2) EP3226147B1 (en)
JP (1) JP6536677B2 (en)
KR (1) KR102092660B1 (en)
CN (2) CN111427827B (en)
AU (1) AU2015412144B2 (en)
BR (1) BR112017008407B1 (en)
CA (1) CA2965982C (en)
RU (1) RU2658884C1 (en)
SG (1) SG11201703261WA (en)
WO (1) WO2017113128A1 (en)
ZA (1) ZA201702790B (en)

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CN107526617B (en) * 2017-09-04 2020-12-29 井冈山电器有限公司 CPU updating method and system
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Also Published As

Publication number Publication date
BR112017008407A8 (en) 2022-10-18
EP3575977A1 (en) 2019-12-04
JP6536677B2 (en) 2019-07-03
BR112017008407A2 (en) 2017-12-19
WO2017113128A1 (en) 2017-07-06
EP3226147A4 (en) 2017-12-27
EP3226147B1 (en) 2019-12-04
CN106104505A (en) 2016-11-09
BR112017008407B1 (en) 2023-04-04
CA2965982C (en) 2019-02-12
CA2965982A1 (en) 2017-06-29
RU2658884C1 (en) 2018-06-25
EP3226147A1 (en) 2017-10-04
CN106104505B (en) 2020-02-21
ZA201702790B (en) 2019-12-18
KR20170093116A (en) 2017-08-14
US11138147B2 (en) 2021-10-05
CN111427827A (en) 2020-07-17
CN111427827B (en) 2023-03-17
JP2018507454A (en) 2018-03-15
KR102092660B1 (en) 2020-03-24
AU2015412144A1 (en) 2017-07-13
US20170364475A1 (en) 2017-12-21
AU2015412144B2 (en) 2018-11-15

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