BR112016025031B1 - Método e sistema para minimizar consumo de potência em processamento de quadro gráfico e memória legível por computador - Google Patents

Método e sistema para minimizar consumo de potência em processamento de quadro gráfico e memória legível por computador Download PDF

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Publication number
BR112016025031B1
BR112016025031B1 BR112016025031-1A BR112016025031A BR112016025031B1 BR 112016025031 B1 BR112016025031 B1 BR 112016025031B1 BR 112016025031 A BR112016025031 A BR 112016025031A BR 112016025031 B1 BR112016025031 B1 BR 112016025031B1
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BR
Brazil
Prior art keywords
cpu
gpu
dcvs
workload
data
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BR112016025031-1A
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English (en)
Portuguese (pt)
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BR112016025031A2 (pt
Inventor
Hee Jun Park
Young Hoon Kang
Mriganka Mondal
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Qualcomm Incorporated
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Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Publication of BR112016025031A2 publication Critical patent/BR112016025031A2/pt
Publication of BR112016025031B1 publication Critical patent/BR112016025031B1/pt

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/20—Cooling means
    • G06F1/206—Cooling means comprising thermal management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3228—Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/06—Use of more than one graphics processor to process data before displaying to one or more screens
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Human Computer Interaction (AREA)
  • Software Systems (AREA)
  • Power Sources (AREA)
BR112016025031-1A 2014-04-30 2015-04-29 Método e sistema para minimizar consumo de potência em processamento de quadro gráfico e memória legível por computador BR112016025031B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/266,685 2014-04-30
US14/266,685 US9378536B2 (en) 2014-04-30 2014-04-30 CPU/GPU DCVS co-optimization for reducing power consumption in graphics frame processing
PCT/US2015/028098 WO2015168189A1 (en) 2014-04-30 2015-04-29 Cpu/gpu dcvs co-optimization for reducing power consumption in graphics frame processing

Publications (2)

Publication Number Publication Date
BR112016025031A2 BR112016025031A2 (pt) 2017-08-15
BR112016025031B1 true BR112016025031B1 (pt) 2022-09-20

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BR112016025031-1A BR112016025031B1 (pt) 2014-04-30 2015-04-29 Método e sistema para minimizar consumo de potência em processamento de quadro gráfico e memória legível por computador

Country Status (7)

Country Link
US (1) US9378536B2 (enExample)
EP (1) EP3137965B1 (enExample)
JP (1) JP6412162B2 (enExample)
KR (1) KR102380576B1 (enExample)
CN (1) CN106258011B (enExample)
BR (1) BR112016025031B1 (enExample)
WO (1) WO2015168189A1 (enExample)

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Also Published As

Publication number Publication date
JP6412162B2 (ja) 2018-10-24
CN106258011B (zh) 2019-07-12
WO2015168189A1 (en) 2015-11-05
US9378536B2 (en) 2016-06-28
CN106258011A (zh) 2016-12-28
KR20160147964A (ko) 2016-12-23
KR102380576B1 (ko) 2022-03-29
EP3137965B1 (en) 2019-02-20
BR112016025031A2 (pt) 2017-08-15
US20150317762A1 (en) 2015-11-05
EP3137965A1 (en) 2017-03-08
JP2017515230A (ja) 2017-06-08

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