WO2018129708A1

WO2018129708A1 - Determining processor utilization of multiprocessing system

Info

Publication number: WO2018129708A1
Application number: PCT/CN2017/071099
Authority: WO
Inventors: Chow Kingsum; Wanyi ZHU; Chengdong LI
Original assignee: Alibaba Group Holding Limited
Priority date: 2017-01-13
Filing date: 2017-01-13
Publication date: 2018-07-19
Also published as: CN110235085A

Abstract

The techniques described herein provide a solution for determining CPU usage of a multiprocessing processor core. CPU usage of multiple logical processors of a processor core are determined. The CPU usage of the processor core is estimated based on a higher usage metric among the multiple logical processors. The lowest CPU usage metric among the multiple logical processors will not be used in estimating the CPU usage of the processor core.

Description

DETERMINING PROCESSOR UTILIZATION OF MULTIPROCESSING SYSTEM

BACKGROUND

Multiprocessing refers to the use of multiple processing components within a single computing system and/or the capacity of a system to support multiple processes and/or threads and allocate the processes and/or threads among multiple processing components. A multi-core processor is a single computing component with multiple (commonly even number of) independent physical processor cores. The multiple cores are either fabricated onto a single integrated circuit die (known as a chip multiprocessor or CMP) , or onto multiple dies in a single chip package. Multithreading is a processor design/ability where a single processor or a single processor core of a multi-core processor to execute multiple threads simultaneously. In multithreading, the multiple threads share the resources of a single processor core, e.g., the computing units, the cache, and the translation lookaside buffer (TLB) . From system design perspective, a processor core with the capacity of executing multiple program threads is called a multi-threading processor core and each such capacity is called a logical processor or a hardware thread as compared to an actual program thread executed in the “hardware thread. ”

CPU utilizations obtained from operation systems (OS) are common metrics that have been used for many purposes like product sizing, computer capacity planning, job scheduling, etc. However, with the advances in computer architecture designs including multi-processing systems, and especially hyper-threading, the CPU utilization as reported by the operating systems may be unreliable.

BRIEF DESCRIPTION OF THE DRAWINGS

To describe technical solutions in the embodiments of the present disclosure more clearly, the accompanying drawings are briefly described herein. The accompanying drawings described herein merely represent some embodiments of the present disclosure, and one of ordinary skill in the art may further derive other drawings from these accompanying drawings without making any creative effort. The use of the same reference numbers in different figures indicates similar or identical items.

FIGURE 1 illustrates an example multiprocessing system.

FIGURE 2 illustrates an example system for determining processor utilization and allocating computing resources.

FIGURE 3 illustrates an example operation environment of the example system of FIGURE 2.

FIGURE 4 illustrates an example operation process for determining processor utilization and allocating computing resources.

FIGURE 5 illustrates an example computer architecture diagram illustrating an illustrative computer hardware and software architecture for a computing system capable of implementing aspects of the techniques and technologies presented herein.

FIGURE 6 illustrates a diagram illustrating an example distributed computing environment capable of implementing aspects of the techniques and technologies presented herein.

FIGURE 7 illustrates a computer architecture diagram illustrating an example computing device architecture for a computing device capable of implementing aspects of the techniques and technologies presented herein.

DETAILED DESCRIPTION

The disclosure provides a solution to determine a processor utilization of a multiple processing system and to allocate computing resources based on the determined processor utilization. In the following detailed description, references are made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific configurations or examples, in which like numerals represent like elements throughout the several figures.

FIGURE 1 illustrates an example multiprocessing system 100 including an example symmetric multi-core processing unit 105 ( “processing unit 105” ) including multiple (here for example, four) processor cores 110, each having their own caches “L1 caches” 120. Processor cores 110 also share a cache “L2 cache” 130. Each of processor cores 110 includes multi-threading capacity through multiple (here for illustrative example, two) hardware threads 140. In the description herein, processing unit 105 and the components and operations thereof are used as an example to illustrate the current technical solution for determining processor utilization. It should be appreciated that the scope of the disclosure shall not be limited to the specific architecture of multiprocessing system 100 and/or processing unit 105 or any other specific multi-processing system architecture. For example, processor core 110 could be a lower level processor or CPU. In this disclosure, the term “processor” and “CPU” are used interchangeably and do not have any variation in definition and interpretation. Further, multiprocessing system 100 may include multiple tiers of multiprocessing unit 105 such that each processor core 110 itself may be a lower level multiprocessing unit 105 and/or each multiprocessing unit 105 may be a processor core 110 of a higher level multiprocessing unit 105. For example, multiprocessing system 100 may include a hierarchical clustering structure with tight coupling of multiprocessing components (e.g., processing units 105 and/or processor cores 110) within a cluster. In another example, multiprocessing system 100 and/or processing unit 105 may be a virtual machine capable of virtual symmetric multiprocessing. In another example, multiprocessing system 100 is a symmetric multiprocessing system including multiple tiers of processing units 105 and processor cores 110. All now existing and future developed multiprocessing systems and architectures could be used with the current disclosure to determine processor utilization and to allocate computing resources, and all are included in the disclosure.

In the description herein, a “processor core” refers to any computing component that have multithreading capacity and/or multithreading processing, and a “processing unit” references a multiprocessing computing component having multiple processor cores. The terms “processor usage/utilization” and “CPU usage/utilization” are used interchangeably and all refer to a metric that indicates an amount of time that a processor is used during a certain period of time, usually represented as a percentage.

1. Example Systems and Environments

FIGURE 2 illustrates a system diagram showing aspects of one illustrative example system disclosed herein for determining processor utilization and allocating computing resources. As shown in FIGURE 2, a processor utilization determination system 200 (hereinafter “system 200” ) may include a multiprocessing system mapping unit 210, a thread CPU usage determination unit 220, a processor core CPU usage determination unit 230, a processing unit CPU usage determination unit 240 and a computing resource allocating unit 250. Multiprocessing system mapping unit 210 may further include a controller 212. Thread CPU usage determination unit 220 may further include a sampling interval determination unit 222. System 200 may also include a user interface 260 and other components.

It should be appreciated that units of system 200 may reside in a single computing device, e.g., a PC, or in multiple computing devices in a distributed computing environment/system, and all are included in the disclosure. Details of a computing device or a distributed computing environment will be further described in the disclosure.

In operation, multiprocessing system mapping unit 210 is configured to identify multiple hardware threads 140 of a processor core 110 of a computing system where processing unit 105 resides. As hardware threads 140 can be assigned to execute software threads by an operation system in different manners, a mapping of how a processor core 110 is shared by hardware threads 140 in the operation may be performed to facilitate determining processor utilization. For example, a processor core 110 of multithreading capacity may or may not engage in a multithreading operation. For different operation systems, various approaches may be used to identify hardware threads 140 of a processor core (s) 110. For example, in the case of a Linux system, the command /proc/cpuinfo may be used to lookup hardware threads 140 and how processor cores 110 are shared by hardware threads 140. It shall be appreciated that any now existing and future developed approaches may be used to identify hardware threads 140 of a processor core 110 and all are included in the disclosure.

Thread CPU usage determination unit 120 is configured to determine a usage metric for each of multiple hardware thread 140 of a processor core 110. Any metric to indicate a processor usage of a hardware thread may be used by thread CPU usage determination unit 120 and all are included in the disclosure. For example, thread CPU usage determination unit 120 may consult with the operation system’s thread state counter to determine the thread state of a hardware thread 140. In another example, thread CPU usage determination unit 120 may communicate to an operating system’s performance monitoring tool, e.g., a performance monitoring unit (PMU) and/or a performance monitoring counter (PMC) , to determine the CPU usage of a hardware thread 140. For another example, the “KernelTime” and “UserTime” obtained through a “GetProcessTimes” function may be used to determine the CPU usage of a hardware thread 140.

As multiple hardware threads 140 share a processor core 110, a program thread executed in one hardware thread 140 may migrate to another hardware thread 140 sharing the same processor core 100. Such migration of program threads between/among multiple hardware threads 140 may complicate the determination of CPU usage of each of the multiple hardware threads 140. To solve, among others, this issue, sampling interval determination unit 222 is configured to determine a sampling interval that is smaller than a threshold time interval during which a program (software) thread may migrate from one hardware thread 140 to another hardware thread 140 of the multiple hardware threads 140 of a shared processor core 110. The sampling interval and/or the threshold time interval may be predetermined using experimental data and/or may be dynamically determined/adjusted in substantially real time. Further, the type of program threads/process executed in the hardware threads 140 may also be considered in determining the sampling interval and/or the threshold time interval.

Processor core CPU usage determination unit 230 is configured to estimate a usage metric of a processor core 110 based on a higher usage metric among multiple hardware threads 140 of the processor core 110. Here, processor core CPU usage determination unit 230 may only use a higher CPU usage metric (s) , but does not use a lower CPU usage metric determined for the multiple hardware threads 140 of the processor core 110. A higher CPU usage metric is defined relative to a lower CPU usage metric and does not indicate any absolute CPU usage metric value. For example, in a scenario that a processor core 110 is shared by two hardware threads 140, with determined CPU usage metrics 70％and 30％respectively. CPU usage metric 70％is higher than 30％and processor core CPU usage determination unit 230 may only use the higher 70％CPU usage metric to estimate the CPU usage metric of the processor core 110. There are various approaches to identify a higher CPU usage metric among multiple hardware threads 140, and all are included in the disclosure. For example, in the scenario of multiple determined CPU usage metrics of hardware threads 140, processor core CPU usage determination unit 230 may identify all but the lowest CPU usage metric as higher CPU usage metrics. Processor core CPU usage determination unit 230 may also identify only the highest determined CPU usage metric as the higher CPU usage metric among multiple hardware threads 140 to be used in estimating the CPU usage metric of processor core 110. In an extreme scenario where all determined CPU usage metrics among the multiple hardware threads 140 are the same, processor core CPU usage determination unit 230 may use the same CPU usage metric as the higher one.

There are various approaches processor core CPU usage determination unit 230 may take to estimate a CPU usage metric of a processor core 110 using the identified higher CPU usage metric (s) of hardware threads 140, and all are included in the disclosure. In an example, processor core CPU usage determination unit 230 may estimate a usage metric of the processor core 110 based on the highest usage metric among the multiple hardware threads 140. For example, the highest CPU usage metric of the multiple hardware threads 140 may be taken as the CPU usage metric of the processor core 110. In another example, processor core CPU usage determination unit 230 may estimate a usage metric of the processor core 110 based on averaging multiple higher usage metrics among the multiple hardware threads 140. For an illustrative example, a processor core 110 may include four hardware threads 140 with determined CPU usage metrics of 80％, 70％, 50％and 0 respectively. Processor core CPU usage determination unit 230 may identify the 80％and 70％CPU usage metrics as the higher CPU usage metrics among the four hardware threads 140 and use the average between 80％and 70％, i.e., 75％, as the estimated CPU usage metric of processor core 110.

Processing unit CPU usage determination unit 240 is configured to determine a usage metric of a processing unit 105 based on the estimated usage metrics of the multiple processor cores 110. In an example, processing unit CPU usage determination unit 240 may determine the usage metric of the processing unit 105 by averaging the estimated usage metrics of the multiple processor cores 110 of the processing unit 105. In another example, processing unit CPU usage determination unit 240 may determine the usage metric of the processing unit 105 based on a higher estimated usage metric among the multiple processor cores 110. Similar to processor core CPU usage determination unit 230, processing unit CPU usage determination unit 240 may determine the processor usage of processing unit 105 based on the highest usage metric among the multiple processor cores 110. In another example, processing unit CPU usage determination unit 240 may determine the usage metric of processing unit 105 based on averaging multiple higher usage metrics among the multiple processor cores 110.

Computing resource allocating unit 250 is configured to allocate computing resources of a computing system where processor cores 110 reside based on the estimated usage metrics of processor cores 110. The allocation may be directly based on the estimated usage metric of processor cores 110 and/or may be based indirectly on the estimated usage metric of processor cores 110 through the determined usage of processing unit 105 containing processor cores 110. In an example, computing resource allocating unit 250 may apply rules in the allocation of computing resources. The rules may provide various manners of allocating computing resources in different applications. For example, in the case of data center application, computing resource allocating unit 250 may apply a rule to allocate the computing resources more conservatively. Rules may also be provided to processor core CPU usage determination unit 230 and/or processing unit CPU usage determination unit 240 in the relevant operations. For example, in the case of data center application, the rules may provide that processor core CPU usage determination unit 230 estimates the usage of the processor core 110 based on the highest usage metric among the multiple hardware threads 140 so that the processor core CPU usage is estimated in a more conservative way.

FIGURE 3 illustrates an operation environment 300 of system 200. System 200 is configured to communicate with computing systems 310 through network 320. Each computing system 310 includes one or more multiprocessing system 100 including processing units 105. Multiprocessing systems 310 may include different multiprocessing architectures and all are included in the disclosure. System 200 or any of the components thereof may physically reside in one or more of computing systems 310 or may reside in a separate computing system (s) . Environment 300 may also include a resource 330 which system 200 may take advantage of in its operations. For example, resource 330 may provide cloud based data storage for system 200 and may provide rules in the operation of system 200, e.g., the rules used in the operation of computing resource allocating unit 250. In operation, system 200 is configured to determine the CPU usage of the processing unit/processor cores of multiprocessing system 100 of computing systems 310 and allocate computing resources of computing systems 310 based on the determined CPU usage.

2. Example Operation Flows

Referring now to FIGURE 4, which illustrates an example flow chart of a process 400 of an example operation of system 200. In example operation 410, multiprocessing system mapping unit 210 may map a multiprocessing system 100 to identify the architectures of a processing unit (s) 105, processor core (s) 110, and hardware threads 140. Specifically, in example sub-operation 412, multiprocessing system mapping unit 210 may identify multiple hardware threads 140 of a processor core 110 of a computing system 310 where processing unit 105 resides. It shall be appreciated that any now existing and future developed approaches may be used to identify hardware threads 140 of a processor core 110 and all are included in the disclosure. For example, information may be received from a thread controller to identify hardware threads 140 of a processor core 110. In an example, a criterion to identify multiple hardware threads 140 of a processor core 110 includes determining that the hardware threads 140 share a hardware resource, e.g., L1 cache 120, of the processor core 110.

In example operation 420, thread CPU usage determination unit 220 may determine a usage metric for each of multiple hardware thread 140 of a processor core 110. Any metric to indicate a processor usage of a hardware thread 140 may be used by thread CPU usage determination unit 220 and all are included in the disclosure. Specifically, in sub-operation 422, sampling interval determination unit 222 may determine a sampling interval that is smaller than a threshold time interval during which a program (software) thread may migrate from one hardware thread to another hardware thread of the multiple hardware threads 140 of a shared processor core 110. The sampling interval and/or the threshold time interval may be predetermined using experimental data and/or may be dynamically determined/adjusted in substantially real time. Further, the type of program threads/processes executed in the hardware threads 140 may also be considered in determining the sampling interval and/or the threshold time interval. Sampling interval determination unit 222 may also receive the threshold time interval from resource 330. CPU usage of hardware threads 140 may be determined under the determined sampling interval.

In example operation 430, processor core CPU usage determination unit 230 may estimate a usage metric of a processor core 110 based on a higher usage metric among multiple hardware threads 140 of the processor core 110. Processor core CPU usage determination unit 230 only uses a higher CPU usage metric (s) , but does not use a lower CPU usage metric determined for the multiple hardware threads 140 of the processor core 110. A higher CPU usage metric is only relative to a lower CPU usage metric and does not indicate any absolute CPU usage metric value. There are various approaches to identify a higher CPU usage metric (s) among multiple hardware threads 140, and all are included in the disclosure. For example, in the scenario of multiple determined CPU usage metrics of hardware threads 140, processor core CPU usage determination unit 230 may identify all but the lowest CPU usage metric as the higher CPU usage metrics. Processor core CPU usage determination unit 230 may also identify only the highest determined CPU usage metric among multiple hardware threads 140 as the higher CPU usage metric to be used in estimating the CPU usage metric of processor core 110. In an extreme scenario where all determined CPU usage metrics among the multiple hardware threads 140 are the same, processor core CPU usage determination unit 230 may use the same CPU usage metric as the higher one.

There are various approaches that processor core CPU usage determination unit 230 may take to estimate a CPU usage metric of a processor core 110 using the identified higher CPU usage metric (s) of hardware threads 140, and all are included in the disclosure. In one example, processor core CPU usage determination unit 230 may estimate the usage of the processor core 110 based on the highest usage metric among the multiple hardware threads 140. For example, the highest CPU usage metric of the multiple hardware threads 140 may be taken as the CPU usage metric of the processor core 110. In another example, processor core CPU usage determination unit 230 may estimate the usage metric of processor core 110 based on averaging multiple higher usage metrics among the multiple hardware threads 140.

In an example, processor core CPU usage determination unit 230 may receive a rule (s) from computing resource allocating unit 250 in identifying a higher usage metric among the hardware threads 140 and/or in estimating the CPU usage of processor core 110. The received rule (s) may depend on applications/processes executed in the relevant computing system (s) 310. For example, in the scenario of computing systems 310 executing data center applications, the rules may provide that processor core CPU usage determination unit 230 identify the highest usage metric among the multiple hardware threads 140 sharing a processor core 110 as the higher usage metric and be used as the estimated usage metric of the processor core 110.

In example operation 440, processing unit CPU usage determination unit 240 may determine a usage metric of a processing unit 105 based on the estimated usage metrics of multiple processor cores 110 of the processing unit 105. In an example, processing unit CPU usage determination unit 240 may determine the usage metric of the processing unit 105 by averaging the estimated usage metrics of the multiple processor cores 110. In another example, processing unit CPU usage determination unit 240 may determine the usage metric of processing unit 105 based on a higher estimated usage metric (s) among the multiple processor cores 110. Similar to processor core CPU usage determination unit 230, processing unit CPU usage determination unit 240 may determine the processor usage of processing unit 105 based on the highest usage metric among the multiple processor cores 110. In another example, processing unit CPU usage determination unit 240 may determine the usage metric of processing unit 105 based on averaging multiple higher usage metrics among the multiple processor cores 110.

In example operation 450, controller 212 of multiprocessing system mapping unit 210 may determine whether there is a higher level processing unit 105, based on the mapping of multiprocessing system 100. If there is no higher level processing unit 105, i.e., the current processing unit 105 is the highest level of the multiprocessing system 100, the operation flow moves to example operation 460. If there is a higher level processing unit (s) 105, the operation flow returns to example operation 440, where processing unit CPU usage determination unit 240 may determine a usage metric of the higher level processing unit 105 based on the usage metrics of multiple lower level processing units 105. As described herein, with respect to a higher level processing unit 105 in a multiprocessing system 100, the lower level processing units 105 may be treated similarly as a processor core 110 in example operation 440.

In example operation 460, computing resource allocating unit 250 is configured to allocate computing resources of a computing system 310 where processor cores 110 resides based on the estimated usage metric of processor cores 110. The allocation may be directly based on the estimated usage metric of processor cores 110 and/or may be based indirectly on the estimated usage metric of processor cores 110 through the determined usage metric of processing unit 105 containing processor cores 110. In an example, computing resource allocating unit 250 may apply rules in the allocation of computing resources. The rules may provide various manners of allocating computing resources in different applications. For example, in the application of data center, computing resource allocating unit 250 may apply a rule to allocate the computing resources more conservatively.

It should be appreciated that the operations of the methods disclosed herein are not necessarily presented in any particular order and that performance of some or all of the operations in an alternative order (s) is possible and is contemplated. The operations have been presented in the demonstrated order for ease of description and illustration. Operations may be added, omitted, and/or performed simultaneously, without departing from the scope of the appended claims.

It also should be appreciated that the illustrated methods can be ended at any time and need not be performed in its entirety. Some or all operations of the methods, and/or substantially equivalent operations, can be performed by execution of computer-readable instructions included on a computer-storage media, as defined below. The term “computer-readable instructions, ” and variants thereof, as used in the description and claims, is used expansively herein to include routines, applications, application modules, program modules, programs, components, data structures, algorithms, and the like. Computer-readable instructions can be implemented on various system configurations, including single-processor or multiprocessor systems, minicomputers, mainframe computers, personal computers, hand-held computing devices, microprocessor-based, programmable consumer electronics, combinations thereof, and the like.

Thus, it should be appreciated that the logical operations described herein are implemented (1) as a sequence of computer implemented acts or program modules running on a computing system and/or (2) as interconnected machine logic circuits or circuit modules within the computing system. The implementation is a matter of choice dependent on the performance and other requirements of the computing system. Accordingly, the logical operations described herein are referred to variously as states, operations, structural devices, acts, or modules. These operations, structural devices, acts, and modules may be implemented in software, in firmware, in special purpose digital logic, and any combination thereof.

As described herein, in conjunction with FIGUREs 2 and 3, the operations of example process 400 are described herein as being implemented, at least in part, by an application, component, and/or circuit. Although the described illustration refers to the components of FIGUREs 1, 2 and 3, it can be appreciated that the operations of the process 400 may be also implemented in many other ways. For example, process 400 may be implemented, at least in part, by computer processor or processor of separate computers. In addition, one or more of the operations of the processes 400 may alternatively or additionally be implemented, at least in part, by a computer working alone or in conjunction with other software modules, such as a server module.

3. Example System Components

A computing device where any one or more of the units of system 200 of FIGURE 2 are located may be in the form of a personal computer, a wearable computing device, a mobile phone, or any other device having components for processing and communicating data. For example, a computing device may be a tablet having one or more user-machine interface such as a display interface and/or an input device. A display interface may include a monitor, a projection surface, a touch screen, and/or any other interface device capable of displaying. In addition, an input device may include a camera, a microphone, a keyboard or any other input device, capable of inputting data to the computing device.

The computing device may also include a local memory that is capable of storing, communicating, and processing input data, output data, and other data. The local memory may also include a program module configured to manage techniques described herein including the one or more of the units of system 200 of FIGURE 2.

FIGURE 5 shows additional details of an example computer architecture 500 for a computer, on which one or more of the units of system 200 of FIGURE 2 may be located, and which is capable of executing the program components including the units of system 200 described herein. Thus, the computer architecture 500 illustrated in FIGURE 5 illustrates an architecture for a server computer, mobile phone, a PDA, a smart phone, a desktop computer, a netbook computer, a tablet computer, and/or a laptop computer. The computer architecture 500 may be utilized to execute any aspects of the software components presented herein.

The computer architecture 500 illustrated in FIGURE 5 includes a central processing unit 502 ( “CPU” ) , a system memory 504, including a random access memory 506 ( “RAM” ) and a read-only memory ( “ROM” ) 508, and a system bus 510 that couples the memory 504 to the CPU 502. A basic input/output system containing the basic routines that help to transfer information between elements within the computer architecture 500, such as during startup, is stored in the ROM 508. The computer architecture 500 further includes a mass storage device 512 for storing an operating system 507, data, such as the output data 509, and one or more application programs.

The mass storage device 512 is connected to the CPU 502 through a mass storage controller (not shown) connected to the bus 510. The mass storage device 512 and its associated computer-readable media provide non-volatile storage for the computer architecture 500. Although the description of computer-readable media contained herein refers to a mass storage device, such as a solid state drive, a hard disk or CD-ROM drive, it should be appreciated by those skilled in the art that computer-readable media can be any available computer storage media or communication media that can be accessed by the computer architecture 500.

Communication media includes computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any delivery media. The term “modulated data signal” means a signal that has one or more of its characteristics changed or set in a manner as to encode information in the signal. By way of example, and without limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, RF, infrared and other wireless media. Combinations of the any of the above should also be included within the scope of computer-readable media.

By way of example, and not limitation, computer storage media may include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules or other data. For example, computer media includes, but is not limited to, RAM, ROM, EPROM, EEPROM, flash memory or other solid state memory technology, CD-ROM, digital versatile disks ( “DVD” ) , HD-DVD, BLU-RAY, or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by the computer architecture 500. For purposes the claims, the phrase “computer storage medium, ” “computer-readable storage medium” and variations thereof, does not include waves, signals, and/or other transitory and/or intangible communication media, per se.

According to various configurations, the computer architecture 500 may operate in a networked environment using logical connections to remote computers through the network 756 and/or another network (not shown) . The computer architecture 500 may connect to the network 756 through a network interface unit 514 connected to the bus 510. It should be appreciated that the network interface unit 514 also may be utilized to connect to other types of networks and remote computer systems. The computer architecture 500 also may include an input/output controller 516 for receiving and processing input from a number of other devices, including a keyboard, mouse, or electronic stylus (not shown in FIGURE 5) . Similarly, the input/output controller 516 may provide output to a display screen, a printer, or other type of output device (also not shown in FIGURE 5) .

It should be appreciated that the software components of system 200 described herein may, when loaded into the CPU 502 and executed, transform the CPU 502 and the overall computer architecture 500 from a general-purpose computing system into a special-purpose computing system customized to facilitate the functionality presented herein. The CPU 502 may be constructed from any number of transistors or other discrete circuit elements, which may individually or collectively assume any number of states. More specifically, the CPU 502 may operate as a finite-state machine, in response to executable instructions contained within the software modules disclosed herein. These computer-executable instructions may transform the CPU 502 by specifying how the CPU 502 transitions between states, thereby transforming the transistors or other discrete hardware elements constituting the CPU 502.

Encoding the software modules presented herein also may transform the physical structure of the computer-readable media presented herein. The specific transformation of physical structure may depend on various factors, in different implementations of this description. Examples of such factors may include, but are not limited to, the technology used to implement the computer-readable media, whether the computer-readable media is characterized as primary or secondary storage, and the like. For example, if the computer-readable media is implemented as semiconductor-based memory, the software disclosed herein may be encoded on the computer-readable media by transforming the physical state of the semiconductor memory. For example, the software may transform the state of transistors, capacitors, or other discrete circuit elements constituting the semiconductor memory. The software also may transform the physical state of such components in order to store data thereupon.

As another example, the computer-readable media disclosed herein may be implemented using magnetic or optical technology. In such implementations, the software presented herein may transform the physical state of magnetic or optical media, when the software is encoded therein. These transformations may include altering the magnetic characteristics of particular locations within given magnetic media. These transformations also may include altering the physical features or characteristics of particular locations within given optical media, to change the optical characteristics of those locations. Other transformations of physical media are possible without departing from the scope and spirit of the present description, with the foregoing examples provided only to facilitate this discussion.

In light of the above, it should be appreciated that many types of physical transformations take place in the computer architecture 500 in order to store and execute the software components presented herein. It also should be appreciated that the computer architecture 500 may include other types of computing devices, including hand-held computers, embedded computer systems, personal digital assistants, and other types of computing devices known to those skilled in the art. It is also contemplated that the computer architecture 500 may not include all of the components shown in FIGURE 5, may include other components that are not explicitly shown in FIGURE 5, or may utilize an architecture completely different than that shown in FIGURE 5.

FIGURE 6 depicts an illustrative distributed computing environment 600 capable of executing the software components of system 200 described herein for determining processor utilization of multiprocessing system 100. Thus, the distributed computing environment 600 illustrated in FIGURE 6 can be utilized to execute any aspects of the software components presented herein. For example, the distributed computing environment 600 can be utilized to execute aspects of the web browser 510, the system 200 and/or any units thereof and/or other software components described herein.

According to various implementations, the distributed computing environment 600 includes a computing environment 602 operating on, in communication with, or as part of the network 604. The network 604 may be or may include the network 756, described above with reference to FIGURE 5. The network 604 also can include various access networks. One or more client devices 606A-606N (hereinafter referred to collectively and/or generically as “clients 606” ) can communicate with the computing environment 602 via the network 604 and/or other connections (not illustrated in FIGURE 6) . In one illustrated configuration, the client devices 606 include a computing device 606A such as a laptop computer, a desktop computer, or other computing device； a slate or tablet computing device ( “tablet computing device” ) 606B； a mobile computing device 606C such as a mobile telephone, a smart phone, or other mobile computing device； a server computer 606D； and/or other devices 606N. It should be understood that any number of clients 606 can communicate with the computing environment 602. Two example computing architectures for the client devices 606 are illustrated and described herein with reference to FIGURES 5 and 7. It should be understood that the illustrated clients 606 and computing architectures illustrated and described herein are illustrative, and should not be construed as being limited in any way.

In the illustrated configuration, the computing environment 602 includes application servers 608, data storage 610, and one or more network interfaces 612. According to various implementations, the functionality of the application servers 608 can be provided by one or more server computers that are executing as part of, or in communication with, the network 604. The application servers 608 can host various services, virtual machines, portals, and/or other resources. In the illustrated configuration, the application servers 608 host one or more virtual machines 614 for hosting applications or other functionality. According to various implementations, the virtual machines 614 host one or more applications and/or software modules for providing intelligent configuration of data visualizations. It should be understood that this configuration is illustrative, and should not be construed as being limiting in any way. The application servers 608 also host or provide access to one or more portals, link pages, Web sites, and/or other information ( “Web portals” ) 616.

According to various implementations, the application servers 608 also include one or more mailbox services 618 and one or more messaging services 620. The mailbox services 618 can include electronic mail ( “email” ) services. The mailbox services 618 also can include various personal information management ( “PIM” ) services including, but not limited to, calendar services, contact management services, collaboration services, and/or other services. The messaging services 620 can include, but are not limited to, instant messaging services, chat services, forum services, and/or other communication services.

The application servers 608 also may include one or more social networking services 622. The social networking services 622 can include various social networking services including, but not limited to, services for sharing or posting status updates, instant messages, links, photos, videos, and/or other information； services for commenting or displaying interest in articles, products, blogs, or other resources； and/or other services.

The social networking services 622 also can include commenting, blogging, and/or micro blogging services. For instance, a social networking application, mail client, messaging client or a browser running on a phone or any other client 606 may communicate with a networking service 622 and facilitate the functionality, even in part, described above with respect to FIGURES 2, 3 and 4.

As shown in FIGURE 6, the application servers 608 also can host other services, applications, portals, and/or other resources ( “other resources” ) 624. The other resources 624 can include, but are not limited to, document sharing, rendering or any other functionality. It thus can be appreciated that the computing environment 602 can provide integration of the concepts and technologies disclosed herein provided herein with various mailbox, messaging, social networking, and/or other services or resources.

As mentioned above, the computing environment 602 can include the data storage 610. According to various implementations, the functionality of the data storage 610 is provided by one or more databases operating on, or in communication with, the network 604. The functionality of the data storage 610 also can be provided by one or more server computers configured to host data for the computing environment 602. The data storage 610 can include, host, or provide one or more real or virtual datastores 626A-626N (hereinafter referred to collectively and/or generically as “datastores 626” ) . The datastores 626 are configured to host data used or created by the application servers 608 and/or other data. Although not illustrated in FIGURE 6, the datastores 626 also can host or store web page documents, word documents, presentation documents, data structures, algorithms for execution by a recommendation engine, and/or other data utilized by any application program or another module, such as the content manager 105. Aspects of the datastores 626 may be associated with a service for storing files.

The computing environment 602 can communicate with, or be accessed by, the network interfaces 612. The network interfaces 612 can include various types of network hardware and software for supporting communications between two or more computing devices including, but not limited to, the clients 606 and the application servers 608. It should be appreciated that the network interfaces 612 also may be utilized to connect to other types of networks and/or computer systems.

It should be understood that the distributed computing environment 600 described herein can provide any aspects of the software elements described herein with any number of virtual computing resources and/or other distributed computing functionality that can be configured to execute any aspects of the software components disclosed herein. According to various implementations of the concepts and technologies disclosed herein, the distributed computing environment 600 provides the software functionality described herein as a service to the clients 606. It should be understood that the clients 606 can include real or virtual machines including, but not limited to, server computers, web servers, personal computers, mobile computing devices, smart phones, and/or other devices. As such, various configurations of the concepts and technologies disclosed herein enable any device configured to access the distributed computing environment 600 to utilize the functionality described herein for providing intelligent configuration of data visualizations, among other aspects. In one specific example, as summarized above, techniques described herein may be implemented, at least in part, by the web browser application 510 of FIGURE 5, which works in conjunction with the application servers 608 of FIGURE 6.

Turning now to FIGURE 7, an illustrative computing device architecture 700 for a computing device that is capable of executing various software components described herein for providing system 200. The computing device architecture 700 is applicable to computing devices that facilitate mobile computing due, in part, to form factor, wireless connectivity, and/or battery-powered operation. In example configurations, the computing devices include, but are not limited to, mobile telephones, tablet devices, slate devices, portable video game devices, and the like. The computing device architecture 700 is applicable to any of the client devices 606 shown in FIGURE 6. Moreover, aspects of the computing device architecture 700 may be applicable to traditional desktop computers, portable computers (e.g., laptops, notebooks, ultra-portables, and netbooks) , server computers, and other computer systems, such as described herein with reference to FIGURE 5. For example, the single touch and multi- touch aspects disclosed herein below may be applied to desktop computers that utilize a touchscreen or some other touch-enabled device, such as a touch-enabled track pad or touch-enabled mouse.

The computing device architecture 700 illustrated in FIGURE 7 includes a processor 702, memory components 704, network connectivity components 706, sensor components 708, input/output components 710, and power components 712. In the illustrated configuration, the processor 702 is in communication with the memory components 704, the network connectivity components 706, the sensor components 708, the input/output ( “I/O” ) components 710, and the power components 712. Although no connections are shown between the individual components illustrated in FIGURE 7, the components can interact to carry out device functions. In some configurations, the components are arranged so as to communicate via one or more busses (not shown) .

The processor 702 includes a central processing unit ( “CPU” ) configured to process data, execute computer-executable instructions of one or more application programs, and communicate with other components of the computing device architecture 700 in order to perform various functionality described herein. The processor 702 may be utilized to execute aspects of the software components presented herein and, particularly, those that utilize, at least in part, a touch-enabled input.

In example configurations, the processor 702 includes a graphics processing unit ( “GPU” ) configured to accelerate operations performed by the CPU, including, but not limited to, operations performed by executing general-purpose scientific and/or engineering computing applications, as well as graphics-intensive computing applications such as high resolution video (e.g., 720P, 1080P, and higher resolution) , video games, three-dimensional ( “3D” ) modeling applications, and the like. In some configurations, the processor 702 is configured to communicate with a discrete GPU (not shown) . In any case, the CPU and GPU may be configured in accordance with a co-processing CPU/GPU computing model, wherein the sequential part of an application executes on the CPU and the computationally-intensive part is accelerated by the GPU.

In example configurations, the processor 702 is, or is included in, a system-on-chip ( “SoC” ) along with one or more of the other components described herein below. For example, the SoC may include the processor 702, a GPU, one or more of the network connectivity components 706, and one or more of the sensor components 708. In some configurations, the processor 702 is fabricated, in part, utilizing a package-on-package ( “PoP” ) integrated circuit packaging technique. The processor 702 may be a single core or multi-core processor.

The processor 702 may be created in accordance with an ARM architecture, available for license from ARM HOLDINGS of Cambridge, United Kingdom. Alternatively, the processor 702 may be created in accordance with an x86 architecture, such as is available from INTEL CORPORATION of Mountain View, California and others.

The memory components 704 include a random access memory ( “RAM” ) 714, a read-only memory ( “ROM” ) 716, an integrated storage memory ( “integrated storage” ) 718, and a removable storage memory ( “removable storage” ) 720. In some configurations, the RAM 714 or a portion thereof, the ROM 716 or a portion thereof, and/or some combination the RAM 714 and the ROM 716 is integrated in the processor 702. In some configurations, the ROM 716 is configured to store a firmware, an operating system or a portion thereof (e.g., operating system kernel) , and/or a bootloader to load an operating system kernel from the integrated storage 718 and/or the removable storage 720.

The integrated storage 718 can include a solid-state memory, a hard disk, or a combination of solid-state memory and a hard disk. The integrated storage 718 may be soldered or otherwise connected to a logic board upon which the processor 702 and other components described herein also may be connected. As such, the integrated storage 718 is integrated in the computing device. The integrated storage 718 is configured to store an operating system or portions thereof, application programs, data, and other software components described herein.

The removable storage 720 can include a solid-state memory, a hard disk, or a combination of solid-state memory and a hard disk. In some configurations, the removable storage 720 is provided in lieu of the integrated storage 718. In other configurations, the removable storage 720 is provided as additional optional storage. In some configurations, the removable storage 720 is logically combined with the integrated storage 718 such that the total available storage is made available as a total combined storage capacity. In some configurations, the total combined capacity of the integrated storage 718 and the removable storage 720 is shown to a user instead of separate storage capacities for the integrated storage 718 and the removable storage 720.

The removable storage 720 is configured to be inserted into a removable storage memory slot (not shown) or other mechanism by which the removable storage 720 is inserted and secured to facilitate a connection over which the removable storage 720 can communicate with other components of the computing device, such as the processor 702. The removable storage 720 may be embodied in various memory card formats including, but not limited to, PC card, CompactFlash card, memory stick, secure digital ( “SD” ) , miniSD, microSD, universal integrated circuit card ( “UICC” ) (e.g., a subscriber identity module ( “SIM” ) or universal SIM ( “USIM” ) ) , a proprietary format, or the like.

It can be understood that one or more of the memory components 704 can store an operating system. According to various configurations, the operating system includes, but is not limited to WINDOWS MOBILE OS from Microsoft Corporation of Redmond, Washington, WINDOWS PHONE OS from Microsoft Corporation, WINDOWS from Microsoft Corporation, PALM WEBOS from Hewlett-Packard Company of Palo Alto, California, BLACKBERRY OS from Research In Motion Limited of Waterloo, Ontario, Canada, IOS from Apple Inc. of Cupertino, California, and ANDROID OS from Google Inc. of Mountain View, California. Other operating systems are contemplated.

The network connectivity components 706 include a wireless wide area network component ( “WWAN component” ) 722, a wireless local area network component ( “WLAN component” ) 724, and a wireless personal area network component ( “WPAN component” ) 726. The network connectivity components 706 facilitate communications to and from the network 756 or another network, which may be a WWAN, a WLAN, or a WPAN. Although only the network 756 is illustrated, the network connectivity components 706 may facilitate simultaneous communication with multiple networks, including the network 604 of FIGURE 7. For example, the network connectivity components 706 may facilitate simultaneous communications with multiple networks via one or more of a WWAN, a WLAN, or a WPAN.

The network 756 may be or may include a WWAN, such as a mobile telecommunications network utilizing one or more mobile telecommunications technologies to provide voice and/or data services to a computing device utilizing the computing device architecture 700 via the WWAN component 722. The mobile telecommunications technologies can include, but are not limited to, Global System for Mobile communications ( “GSM” ) , Code Division Multiple Access ( “CDMA” ) ONE, CDMA7000, Universal Mobile Telecommunications System ( “UMTS” ) , Long Term Evolution ( “LTE” ) , and Worldwide Interoperability for Microwave Access ( “WiMAX” ) . Moreover, the network 756 may utilize various channel access methods (which may or may not be used by the aforementioned standards) including, but not limited to, Time Division Multiple Access ( “TDMA” ) , Frequency Division Multiple Access ( “FDMA” ) , CDMA, wideband CDMA ( “W-CDMA” ) , Orthogonal Frequency Division Multiplexing ( “OFDM” ) , Space Division Multiple Access ( “SDMA” ) , and the like. Data communications may be provided using General Packet Radio Service ( “GPRS” ) , Enhanced Data rates for Global Evolution ( “EDGE” ) , the High-Speed Packet Access ( “HSPA” ) protocol family including High-Speed Downlink Packet Access ( “HSDPA” ) , Enhanced Uplink ( “EUL” ) or otherwise termed High-Speed Uplink Packet Access ( “HSUPA” ) , Evolved HSPA ( “HSPA+” ) , LTE, and various other current and future wireless data access standards. The network 756 may be configured to provide voice and/or data communications with any combination of the above technologies. The network 756 may be configured to or adapted to provide voice and/or data communications in accordance with future generation technologies.

In example configurations, the WWAN component 722 is configured to provide dual-multi-mode connectivity to the network 756. For example, the WWAN component 722 may be configured to provide connectivity to the network 756, wherein the network 756 provides service via GSM and UMTS technologies, or via some other combination of technologies. Alternatively, multiple WWAN components 722 may be utilized to perform such functionality, and/or provide additional functionality to support other non-compatible technologies (i.e., incapable of being supported by a single WWAN component) . The WWAN component 722 may facilitate similar connectivity to multiple networks (e.g., a UMTS network and an LTE network) .

The network 756 may be a WLAN operating in accordance with one or more Institute of Electrical and Electronic Engineers ( “IEEE” ) 802.11 standards, such as IEEE 802.11a, 802.11b, 802.11g, 802.11n, and/or future 802.11 standard (referred to herein collectively as WI-FI) . Draft 802.11 standards are also contemplated. In some configurations, the WLAN is implemented utilizing one or more wireless WI-FI access points. In some configurations, one or more of the wireless WI-FI access points are another computing device with connectivity to a WWAN that are functioning as a WI-FI hotspot. The WLAN component 724 is configured to connect to the network 756 via the WI-FI access points. Such connections may be secured via various encryption technologies including, but not limited, WI-FI Protected Access ( “WPA” ) , WPA2, Wired Equivalent Privacy ( “WEP” ) , and the like.

The network 756 may be a WPAN operating in accordance with Infrared Data Association ( “IrDA” ) , BLUETOOTH, wireless Universal Serial Bus ( “USB” ) , Z-Wave, ZIGBEE, or some other short-range wireless technology. In some configurations, the WPAN component 726 is configured to facilitate communications with other devices, such as peripherals, computers, or other computing devices via the WPAN.

The sensor components 708 include a magnetometer 728, an ambient light sensor 730, a proximity sensor 732, an accelerometer 734, a gyroscope 736, and a Global Positioning System sensor ( “GPS sensor” ) 738. It is contemplated that other sensors, such as, but not limited to, compasses, temperature sensors or shock detection sensors, also may be incorporated in the computing device architecture 700.

The magnetometer 728 is configured to measure the strength and direction of a magnetic field. In some configurations the magnetometer 728 provides measurements to a compass application program stored within one of the memory components 704 in order to provide a user with accurate directions in a frame of reference including the cardinal directions, north, south, east, and west. Similar measurements may be provided to a navigation application program that includes a compass component. Other uses of measurements obtained by the magnetometer 728 are contemplated.

The ambient light sensor 730 is configured to measure ambient light. In some configurations, the ambient light sensor 730 provides measurements to an application program stored within one the memory components 704 in order to automatically adjust the brightness of a display (described below) to compensate for low-light and high-light environments. Other uses of measurements obtained by the ambient light sensor 730 are contemplated.

The proximity sensor 732 is configured to detect the presence of an object or thing in proximity to the computing device without direct contact. In some configurations, the proximity sensor 732 detects the presence of a user’s body (e.g., the user’s face) and provides this information to an application program stored within one of the memory components 704 that utilizes the proximity information to enable or disable some functionality of the computing device. For example, a telephone application program may automatically disable a touchscreen (described below) in response to receiving the proximity information so that the user’s face does not inadvertently end a call or enable/disable other functionality within the telephone application program during the call. Other uses of proximity as detected by the proximity sensor 732 are contemplated.

The accelerometer 734 is configured to measure proper acceleration. In some configurations, output from the accelerometer 734 is used by an application program as an input mechanism to control some functionality of the application program. For example, the application program may be a video game in which a character, a portion thereof, or an object is moved or otherwise manipulated in response to input received via the accelerometer 734. In some configurations, output from the accelerometer 734 is provided to an application program for use in switching between landscape and portrait modes, calculating coordinate acceleration, or detecting a fall. Other uses of the accelerometer 734 are contemplated.

The gyroscope 736 is configured to measure and maintain orientation. In some configurations, output from the gyroscope 736 is used by an application program as an input mechanism to control some functionality of the application program. For example, the gyroscope 736 can be used for accurate recognition of movement within a 3D environment of a video game application or some other application. In some configurations, an application program utilizes output from the gyroscope 736 and the accelerometer 734 to enhance control of some functionality of the application program. Other uses of the gyroscope 736 are contemplated.

The GPS sensor 738 is configured to receive signals from GPS satellites for use in calculating a location. The location calculated by the GPS sensor 738 may be used by any application program that requires or benefits from location information. For example, the location calculated by the GPS sensor 738 may be used with a navigation application program to provide directions from the location to a destination or directions from the destination to the location. Moreover, the GPS sensor 738 may be used to provide location information to an external location-based service, such as E911 service. The GPS sensor 738 may obtain location information generated via WI-FI, WIMAX, and/or cellular triangulation techniques utilizing one or more of the network connectivity components 706 to aid the GPS sensor 738 in obtaining a location fix. The GPS sensor 738 may also be used in Assisted GPS ( “A-GPS” ) systems.

As one should appreciate, one or more of the sensors may be used in detecting contextual information of a user as described in FIGURES 2 and 3.

The I/O components 710 include a display 740, a touchscreen 742, a data I/O interface component ( “data I/O” ) 744, an audio I/O interface component ( “audio I/O” ) 746, a video I/O interface component ( “video I/O” ) 748, and a camera 750. In some configurations, the display 740 and the touchscreen 742 are combined. In some configurations two or more of the data I/O component 744, the audio I/O component 746, and the video I/O component 748 are combined. The I/O components 710 may include discrete processors configured to support the various interface described below, or may include processing functionality built-in to the processor 702.

The display 740 is an output device configured to present information in a visual form. In particular, the display 740 may present graphical user interface ( “GUI” ) elements, text, images, video, notifications, virtual buttons, virtual keyboards, messaging data, Internet content, device status, time, date, calendar data, preferences, map information, location information, and any other information that is capable of being presented in a visual form. In some configurations, the display 740 is a liquid crystal display ( “LCD” ) utilizing any active or passive matrix technology and any backlighting technology (if used) . In some configurations, the display 740 is an organic light emitting diode ( “OLED” ) display. Other display types are contemplated.

The touchscreen 742, also referred to herein as a “touch-enabled screen, ” is an input device configured to detect the presence and location of a touch. The touchscreen 742 may be a resistive touchscreen, a capacitive touchscreen, a surface acoustic wave touchscreen, an infrared touchscreen, an optical imaging touchscreen, a dispersive signal touchscreen, an acoustic pulse recognition touchscreen, or may utilize any other touchscreen technology. In some configurations, the touchscreen 742 is incorporated on top of the display 740 as a transparent layer to enable a user to use one or more touches to interact with objects or other information presented on the display 740. In other configurations, the touchscreen 742 is a touch pad incorporated on a surface of the computing device that does not include the display 740. For example, the computing device may have a touchscreen incorporated on top of the display 740 and a touch pad on a surface opposite the display 740.

In example configurations, the touchscreen 742 is a single-touch touchscreen. In other configurations, the touchscreen 742 is a multi-touch touchscreen. In some configurations, the touchscreen 742 is configured to detect discrete touches, single touch gestures, and/or multi-touch gestures. These are collectively referred to herein as gestures for convenience. Several gestures will now be described. It should be understood that these gestures are illustrative and are not intended to limit the scope of the appended claims. Moreover, the described gestures, additional gestures, and/or alternative gestures may be implemented in software for use with the touchscreen 742. As such, a developer may create gestures that are specific to a particular application program.

In example configurations, the touchscreen 742 supports a tap gesture in which a user taps the touchscreen 742 once on an item presented on the display 740. The tap gesture may be used for various reasons including, but not limited to, opening or launching whatever the user taps. In some configurations, the touchscreen 742 supports a double tap gesture in which a user taps the touchscreen 742 twice on an item presented on the display 740. The double tap gesture may be used for various reasons including, but not limited to, zooming in or zooming out in stages. In some configurations, the touchscreen 742 supports a tap and hold gesture in which a user taps the touchscreen 742 and maintains contact for at least a pre-defined time. The tap and hold gesture may be used for various reasons including, but not limited to, opening a context-specific menu.

In example configurations, the touchscreen 742 supports a pan gesture in which a user places a finger on the touchscreen 742 and maintains contact with the touchscreen 742 while moving the finger on the touchscreen 742. The pan gesture may be used for various reasons including, but not limited to, moving through screens, images, or menus at a controlled rate. Multiple finger pan gestures are also contemplated. In example configurations, the touchscreen 742 supports a flick gesture in which a user swipes a finger in the direction the user wants the screen to move. The flick gesture may be used for various reasons including, but not limited to, scrolling horizontally or vertically through menus or pages. In some configurations, the touchscreen 742 supports a pinch and stretch gesture in which a user makes a pinching motion with two fingers (e.g., thumb and forefinger) on the touchscreen 742 or moves the two fingers apart. The pinch and stretch gesture may be used for various reasons including, but not limited to, zooming gradually in or out of a website, map, or picture.

Although the above gestures have been described with reference to the use one or more fingers for performing the gestures, other appendages such as toes or objects such as styluses may be used to interact with the touchscreen 742. As such, the above gestures should be understood as being illustrative and should not be construed as being limiting in any way.

The data I/O interface component 744 is configured to facilitate input of data to the computing device and output of data from the computing device. In some configurations, the data I/O interface component 744 includes a connector configured to provide wired connectivity between the computing device and a computer system, for example, for synchronization operation purposes. The connector may be a proprietary connector or a standardized connector such as USB, micro-USB, mini-USB, or the like. In some configurations, the connector is a dock connector for docking the computing device with another device such as a docking station, audio device (e.g., a digital music player) , or video device.

The audio I/O interface component 746 is configured to provide audio input and/or output capabilities to the computing device. In some configurations, the audio I/O interface component 746 includes a microphone configured to collect audio signals. In some configurations, the audio I/O interface component 746 includes a headphone jack configured to provide connectivity for headphones or other external speakers. In some configurations, the audio I/O interface component 746 includes a speaker for the output of audio signals. In some configurations, the audio I/O interface component 746 includes an optical audio cable out.

The video I/O interface component 748 is configured to provide video input and/or output capabilities to the computing device. In some configurations, the video I/O interface component 748 includes a video connector configured to receive video as input from another device (e.g., a video media player such as a DVD or BLURAY player) or send video as output to another device (e.g., a monitor, a television, or some other external display) . In some configurations, the video I/O interface component 748 includes a High-Definition Multimedia Interface ( “HDMI” ) , mini-HDMI, micro-HDMI, DisplayPort, or proprietary connector to input/output video content. In some configurations, the video I/O interface component 748 or portions thereof is combined with the audio I/O interface component 746 or portions thereof.

The camera 750 can be configured to capture still images and/or video. The camera 750 may utilize a charge coupled device ( “CCD” ) or a complementary metal oxide semiconductor ( “CMOS” ) image sensor to capture images. In some configurations, the camera 750 includes a flash to aid in taking pictures in low-light environments. Settings for the camera 750 may be implemented as hardware or software buttons.

Although not illustrated, one or more hardware buttons may also be included in the computing device architecture 700. The hardware buttons may be used for controlling some operational aspect of the computing device. The hardware buttons may be dedicated buttons or multi-use buttons. The hardware buttons may be mechanical or sensor-based.

The illustrated power components 712 include one or more batteries 752, which can be connected to a battery gauge 754. The batteries 752 may be rechargeable or disposable. Rechargeable battery types include, but are not limited to, lithium polymer, lithium ion, nickel cadmium, and nickel metal hydride. Each of the batteries 752 may be made of one or more cells.

The battery gauge 754 can be configured to measure battery parameters such as current, voltage, and temperature. In some configurations, the battery gauge 754 is configured to measure the effect of a battery’s discharge rate, temperature, age and other factors to predict remaining life within a certain percentage of error. In some configurations, the battery gauge 754 provides measurements to an application program that is configured to utilize the measurements to present useful power management data to a user. Power management data may include one or more of a percentage of battery used, a percentage of battery remaining, a battery condition, a remaining time, a remaining capacity (e.g., in watt hours) , a current draw, and a voltage.

The power components 712 may also include a power connector, which may be combined with one or more of the aforementioned I/O components 710. The power components 712 may interface with an external power system or charging equipment via an I/O component.

The disclosure presented herein may be considered in view of the following embodiments.

Clause 1: a computer-implemented system for allocating computing resource of a computing system, comprising: one or more processors； and computer readable storage medium communicatively coupled with the one or more processors, the computer readable medium having computer executable instructions stored therein, which when executed, causes the computer-implemented system to: identify multiple hardware threads of a processor core of the computing system； determine a usage metric for each of the multiple hardware threads； estimate a usage metric of the processor core based on the usage metrics of the multiple hardware threads； and output the estimated usage metric of the processor core as a basis for allocating the computing resource of the computing system.

Clause 2: the computer-implemented system of clause 1, wherein the estimating the usage of the processor core is based on the highest usage metric among the multiple hardware threads.

Clause 3: the computer-implemented system of clause 1, wherein the estimating the usage metric of the processor core is based on averaging multiple higher usage metrics among the multiple hardware threads.

Clause 4: the computer-implemented system of clause 1, wherein the determining the usage metric for each of the multiple hardware threads includes determining the usage metric with a sampling interval smaller than a threshold time interval, during which a software thread is capable of migrating from one hardware thread to another hardware thread of the multiple hardware threads.

Clause 5: the computer-implemented system of clause 1, wherein the identifying the multiple hardware threads of the processor core includes determining the multiple hardware threads share a hardware resource of the processor core.

Clause 6: the computer-implemented system of clause 1, wherein the estimating the usage metric of the processor core includes applying a rule.

Clause 7: a method of allocating computing resource of a computing system, comprising: identifying multiple hardware threads of a processor core of the computing system； determining a usage metric for each of the multiple hardware threads； estimating a usage metric of the processor core based on the usage metrics of the multiple hardware threads； and outputting the estimated usage metric of the processor core as a basis for allocating the computing resource of the computing system.

Clause 8: the method of claim 7, further comprising: estimating usage metrics of multiple processor cores of a processing unit of the computing system； determining a usage metric of the processing unit based on the estimated usage metrics of the multiple processor cores； and outputting the usage metric of the processing unit as a basis for allocating the computing resource of the computing system.

Clause 9: the method of clause 8, wherein the determining the usage metric of the processing unit includes averaging the estimated usage metrics of the multiple processor cores.

Clause 10: the method of clause 8, wherein the determining the usage metric of the processing unit is based on a higher estimated usage metric among the multiple processor cores.

Clause 11: the method of clause 7, wherein the estimating the usage of the processor core is based on the highest usage metric among the multiple hardware threads.

Clause 12: the method of clause 7, wherein the estimating the usage metric of the processor core is based on averaging multiple higher usage metrics among the multiple hardware threads.

Clause 13: the method of clause 7, wherein the determining the usage metric for each of the multiple hardware threads includes determining the usage metric with a sampling interval smaller than a threshold time interval, during which a software thread is capable of migrating from one hardware thread to another hardware thread of the multiple hardware threads.

Clause 14: the method of clause 7, wherein the identifying the multiple hardware threads of the processor core includes determining the multiple hardware threads share a hardware resource of the processor core.

Clause 15: the method of clause 7, wherein the computing system includes a symmetric multiprocessing system including multiple tiers of processing units and processor cores.

Clause 16: a computer readable storage medium having computer-executable instructions stored thereupon which, when executed by a computer, cause the computer to perform acts comprising: identifying multiple hardware threads of a processor core of a computing system； determining a usage metric for each of the multiple hardware threads； estimating a usage metric of the processor core based on the usage metric of the multiple hardware threads； and outputting the estimated usage metric of the processor core as a basis for allocating the computing resource of the computing system.

Clause 17: the computer readable storage medium of clause 16, further comprising: estimating usage metrics of multiple processor cores of a processing unit of the computing system； and determining a usage metric of the processing unit based on the estimated usage metrics of the multiple processor cores.

Clause 18: the computer readable storage medium of clause 17, wherein the determining the usage metric of the processing unit includes averaging the estimated usage metrics of the multiple processor cores.

Clause 19: the computer readable storage medium of clause 16, wherein the estimating the usage of the processor core is based on the highest usage metric among the multiple hardware threads.

Clause 20: the computer readable storage medium of clause 16, wherein the estimating the usage metric of the processor core is based on averaging multiple higher usage metrics among the multiple hardware threads.

Clause 21: a computer-implemented system for allocating computing resource of a computing system, comprising: one or more processors； and computer readable storage medium communicatively coupled with the one or more processors, the computer readable medium having computer executable instructions stored therein, which when executed, causes the computer-implemented system to: identify multiple hardware threads of a processor core of the computing system； determine a usage metric for each of the multiple hardware threads； estimate a usage metric of the processor core based on a higher usage metric among the multiple hardware threads； and output the estimated usage metric of the processor core as a basis for allocating the computing resource of the computing system.

Clause 22: a method of allocating computing resource of a computing system, comprising: identifying multiple hardware threads of a processor core of the computing system； determining a usage metric for each of the multiple hardware threads； estimating a usage metric of the processor core based on a higher usage metric among the multiple hardware threads； and outputting the estimated usage metric of the processor core as a basis for allocating the computing resource of the computing system.

Clause 23: a computer readable storage medium having computer-executable instructions stored thereupon which, when executed by a computer, cause the computer to perform acts comprising: identifying multiple hardware threads of a processor core of a computing system； determining a usage metric for each of the multiple hardware threads； estimating a usage metric of the processor core based on a higher usage metric among the multiple hardware threads； and outputting the estimated usage metric of the processor core as a basis for allocating the computing resource of the computing system.

Claims

A computer-implemented system for allocating computing resource of a computing system, comprising:

one or more processors； and

computer readable storage medium communicatively coupled with the one or more processors, the computer readable medium having computer executable instructions stored therein, which when executed, causes the computer-implemented system to:

identify multiple hardware threads of a processor core of the computing system；

determine a usage metric for each of the multiple hardware threads；

estimate a usage metric of the processor core based on the usage metrics of the multiple hardware threads； and

output the estimated usage metric of the processor core as a basis for allocating the computing resource of the computing system.
The computer-implemented system of claim 1, wherein the estimating the usage of the processor core is based on the highest usage metric among the multiple hardware threads.
The computer-implemented system of claim 1, wherein the estimating the usage metric of the processor core is based on averaging multiple higher usage metrics among the multiple hardware threads.
The computer-implemented system of claim 1, wherein the determining the usage metric for each of the multiple hardware threads includes determining the usage metric with a sampling interval smaller than a threshold time interval, during which a software thread is capable of migrating from one hardware thread to another hardware thread of the multiple hardware threads.
The computer-implemented system of claim 1, wherein the identifying the multiple hardware threads of the processor core includes determining the multiple hardware threads share a hardware resource of the processor core.
The computer-implemented system of claim 1, wherein the estimating the usage metric of the processor core includes applying a rule.
A method of allocating computing resource of a computing system, comprising:

identifying multiple hardware threads of a processor core of the computing system；

determining a usage metric for each of the multiple hardware threads；

estimating a usage metric of the processor core based on the usage metrics of the multiple hardware threads； and

outputting the estimated usage metric of the processor core as a basis for allocating the computing resource of the computing system.
The method of claim 7, further comprising:

estimating usage metrics of multiple processor cores of a processing unit of the computing system；

determining a usage metric of the processing unit based on the estimated usage metrics of the multiple processor cores； and

outputting the usage metric of the processing unit as a basis for allocating the computing resource of the computing system.
The method of claim 8, wherein the determining the usage metric of the processing unit includes averaging the estimated usage metrics of the multiple processor cores.
The method of claim 8, wherein the determining the usage metric of the processing unit is based on a higher estimated usage metric among the multiple processor cores.
The method of claim 7, wherein the estimating the usage of the processor core is based on the highest usage metric among the multiple hardware threads.
The method of claim 7, wherein the estimating the usage metric of the processor core is based on averaging multiple higher usage metrics among the multiple hardware threads.
The method of claim 7, wherein the determining the usage metric for each of the multiple hardware threads includes determining the usage metric with a sampling interval smaller than a threshold time interval, during which a software thread is capable of migrating from one hardware thread to another hardware thread of the multiple hardware threads.
The method of claim 7, wherein the identifying the multiple hardware threads of the processor core includes determining the multiple hardware threads share a hardware resource of the processor core.
The method of claim 7, wherein the computing system includes a symmetric multiprocessing system including multiple tiers of processing units and processor cores.
A computer readable storage medium having computer-executable instructions stored thereupon which, when executed by a computer, cause the computer to perform acts comprising:

identifying multiple hardware threads of a processor core of a computing system；

determining a usage metric for each of the multiple hardware threads；

estimating a usage metric of the processor core based on the usage metric of the multiple hardware threads； and

outputting the estimated usage metric of the processor core as a basis for allocating the computing resource of the computing system.
The computer readable storage medium of claim 16, further comprising:

estimating usage metrics of multiple processor cores of a processing unit of the computing system； and

determining a usage metric of the processing unit based on the estimated usage metrics of the multiple processor cores.
The computer readable storage medium of claim 17, wherein the determining the usage metric of the processing unit includes averaging the estimated usage metrics of the multiple processor cores.
The computer readable storage medium of claim 16, wherein the estimating the usage of the processor core is based on the highest usage metric among the multiple hardware threads.
The computer readable storage medium of claim 16, wherein the estimating the usage metric of the processor core is based on averaging multiple higher usage metrics among the multiple hardware threads.