BR112015028033A2 - método para melhorar largura de banda em dispositivos de memória empilhados - Google Patents

método para melhorar largura de banda em dispositivos de memória empilhados

Info

Publication number
BR112015028033A2
BR112015028033A2 BR112015028033A BR112015028033A BR112015028033A2 BR 112015028033 A2 BR112015028033 A2 BR 112015028033A2 BR 112015028033 A BR112015028033 A BR 112015028033A BR 112015028033 A BR112015028033 A BR 112015028033A BR 112015028033 A2 BR112015028033 A2 BR 112015028033A2
Authority
BR
Brazil
Prior art keywords
memory device
memory
stacked
bandwidth
stacked memory
Prior art date
Application number
BR112015028033A
Other languages
English (en)
Inventor
D Vogt Pete
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR112015028033A2 publication Critical patent/BR112015028033A2/pt

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1003—Interface circuits for daisy chain or ring bus memory arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Computer Hardware Design (AREA)

Abstract

resumo patente de invenção: "método para melhorar largura de banda em dispositivos de memória empilhados". a invenção refere-se a um aparelho e métodos de aumento da taxa de dados e largura de banda de memória de sistema que inclui matriz de dispositivo de memória empilhada. a memória de sistema inclui um dispositivo de memória que tem uma pluralidade de matrizes de dispositivo de memória em uma configuração empilhada, um controlador de memória acoplado à matriz de dispositivo de memória empilhada e um barramento de dados particionado. as matrizes de dispositivo de memória incluem, cada uma, um, dois ou mais grupos de bancos de memória. configurando-se cada matriz de dispositivo de memória para entregar toda sua largura de banda por uma partição única diferente do canal de dados, a memória de sistema pode conseguir uma taxa de dados e uma largura de banda aumentadas sem aumentar significativamente os custos sobre configurações típicas de memória de sistema que incluem matriz de dispositivo de memória empilhada.
BR112015028033A 2013-06-10 2014-05-29 método para melhorar largura de banda em dispositivos de memória empilhados BR112015028033A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/913,628 US8964443B2 (en) 2013-06-10 2013-06-10 Method for improving bandwidth in stacked memory devices
PCT/US2014/039944 WO2014200701A1 (en) 2013-06-10 2014-05-29 Method for improving bandwidth in stacked memory devices

Publications (1)

Publication Number Publication Date
BR112015028033A2 true BR112015028033A2 (pt) 2017-07-25

Family

ID=52005352

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112015028033A BR112015028033A2 (pt) 2013-06-10 2014-05-29 método para melhorar largura de banda em dispositivos de memória empilhados

Country Status (8)

Country Link
US (1) US8964443B2 (pt)
EP (1) EP3008730B1 (pt)
JP (1) JP6028295B2 (pt)
KR (1) KR101746325B1 (pt)
CN (1) CN105190758B (pt)
BR (1) BR112015028033A2 (pt)
RU (1) RU2636670C2 (pt)
WO (1) WO2014200701A1 (pt)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10360972B2 (en) 2015-03-10 2019-07-23 Rambus Inc. Memories and memory components with interconnected and redundant data interfaces
US9870325B2 (en) 2015-05-19 2018-01-16 Intel Corporation Common die implementation for memory devices with independent interface paths
KR102468698B1 (ko) * 2015-12-23 2022-11-22 에스케이하이닉스 주식회사 메모리 장치
US10996890B2 (en) 2018-12-19 2021-05-04 Micron Technology, Inc. Memory module interfaces
CN110164487A (zh) * 2019-04-08 2019-08-23 苏州汇峰微电子有限公司 一种动态随机存储器的架构
US11308017B2 (en) * 2019-05-31 2022-04-19 Micron Technology, Inc. Reconfigurable channel interfaces for memory devices

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU1316047A1 (ru) * 1986-01-06 1987-06-07 Северо-Западный Заочный Политехнический Институт Логическое запоминающее устройство
JP4419049B2 (ja) * 2003-04-21 2010-02-24 エルピーダメモリ株式会社 メモリモジュール及びメモリシステム
US7200021B2 (en) 2004-12-10 2007-04-03 Infineon Technologies Ag Stacked DRAM memory chip for a dual inline memory module (DIMM)
KR100805696B1 (ko) 2005-09-29 2008-02-21 주식회사 하이닉스반도체 반도체 메모리 장치
US7652922B2 (en) * 2005-09-30 2010-01-26 Mosaid Technologies Incorporated Multiple independent serial link memory
JP4828251B2 (ja) * 2006-02-22 2011-11-30 エルピーダメモリ株式会社 積層型半導体記憶装置及びその制御方法
JP2008140220A (ja) * 2006-12-04 2008-06-19 Nec Corp 半導体装置
US8018752B2 (en) * 2009-03-23 2011-09-13 Micron Technology, Inc. Configurable bandwidth memory devices and methods
WO2010117535A2 (en) * 2009-03-30 2010-10-14 Rambus Inc. Memory system, controller and device that supports a merged memory command protocol
JP2011081885A (ja) * 2009-10-09 2011-04-21 Elpida Memory Inc 半導体装置及びその制御方法並びにデータ処理システム
JP5654855B2 (ja) * 2010-11-30 2015-01-14 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置
KR20130011138A (ko) * 2011-07-20 2013-01-30 삼성전자주식회사 모노 랭크와 멀티 랭크로 호환 가능한 메모리 장치
US8437164B1 (en) 2011-07-27 2013-05-07 Apple Inc. Stacked memory device for a configurable bandwidth memory interface
US9117496B2 (en) * 2012-01-30 2015-08-25 Rambus Inc. Memory device comprising programmable command-and-address and/or data interfaces

Also Published As

Publication number Publication date
EP3008730A4 (en) 2017-02-15
US20140362630A1 (en) 2014-12-11
EP3008730B1 (en) 2020-04-01
WO2014200701A1 (en) 2014-12-18
JP2016517995A (ja) 2016-06-20
CN105190758A (zh) 2015-12-23
EP3008730A1 (en) 2016-04-20
CN105190758B (zh) 2018-07-03
RU2015148286A (ru) 2017-05-15
RU2636670C2 (ru) 2017-11-27
KR20150133277A (ko) 2015-11-27
US8964443B2 (en) 2015-02-24
JP6028295B2 (ja) 2016-11-16
KR101746325B1 (ko) 2017-06-12

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Legal Events

Date Code Title Description
B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B350 Update of information on the portal [chapter 15.35 patent gazette]
B06A Patent application procedure suspended [chapter 6.1 patent gazette]
B11B Dismissal acc. art. 36, par 1 of ipl - no reply within 90 days to fullfil the necessary requirements