BR112015027135A2 - dispositivo e método de processamento de dados - Google Patents
dispositivo e método de processamento de dadosInfo
- Publication number
- BR112015027135A2 BR112015027135A2 BR112015027135A BR112015027135A BR112015027135A2 BR 112015027135 A2 BR112015027135 A2 BR 112015027135A2 BR 112015027135 A BR112015027135 A BR 112015027135A BR 112015027135 A BR112015027135 A BR 112015027135A BR 112015027135 A2 BR112015027135 A2 BR 112015027135A2
- Authority
- BR
- Brazil
- Prior art keywords
- bits
- code
- data processing
- data
- bit
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1108—Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/19—Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
- H03M13/2707—Simple row-column interleaver, i.e. pure block interleaving
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
- H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
- H03M13/356—Unequal error protection [UEP]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/615—Use of computational or mathematical techniques
- H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6522—Intended application, e.g. transmission or communication standard
- H03M13/6552—DVB-T2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6522—Intended application, e.g. transmission or communication standard
- H03M13/6555—DVB-C2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0064—Concatenated codes
- H04L1/0065—Serial concatenated codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/007—Unequal error protection
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Mathematical Physics (AREA)
- Mathematical Analysis (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Optimization (AREA)
- Computational Mathematics (AREA)
- Pure & Applied Mathematics (AREA)
- Multimedia (AREA)
- Algebra (AREA)
- Computing Systems (AREA)
- Error Detection And Correction (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
1 / 1 resumo âdispositivo e mãtodo de processamento de dadosâ a presente invenã§ã£o refere-se a: um dispositivo de processamento de dados capaz de garantir boa qualidade de comunicaã§ãµes durante a transmissã£o de dados usando cã³digo ldpc; e a um mã©todo de processamento de dados. em um dispositivo de transmissã£o, cada um dos bits b0, b1 e b2 ã© substituãdo por y1, y0 e y2, respectivamente, quando bits de cã³digo de 3 bits armazenados em unidades de armazenamento que tãªm capacidade de armazenamento de 3 x 16.200/3 bits e lidos um bit de cada vez a partir de cada unidade de armazenamento forem atribuãdos a um sãmbolo, durante a substituiã§ã£o dos bits de cã³digo para cã³digo ldpc que tem um comprimento de cã³digo de 16.200 bits e uma taxa de codificaã§ã£o de 7/15 com bits de sãmbolo para sãmbolos correspondentes a qualquer um dentre oito pontos de sinal prescritos por 8psk. as posiã§ãµes de bits de cã³digo substituãdos, obtidos a partir de dados enviados pelo dispositivo de transmissã£o, sã£o retornadas para as posiã§ãµes originais. a presente invenã§ã£o ã© aplicã¡vel, por exemplo, em transmissã£o de dados, etc., usando cã³digo ldpc
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013-096993 | 2013-05-02 | ||
JP2013096993 | 2013-05-02 | ||
PCT/JP2014/061153 WO2014178297A1 (ja) | 2013-05-02 | 2014-04-21 | データ処理装置、及びデータ処理方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
BR112015027135A2 true BR112015027135A2 (pt) | 2017-07-25 |
BR112015027135B1 BR112015027135B1 (pt) | 2022-02-15 |
Family
ID=51843431
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR112015027135-9A BR112015027135B1 (pt) | 2013-05-02 | 2014-04-21 | Dispositivo e método de processamento de dados |
Country Status (11)
Country | Link |
---|---|
US (1) | US9806742B2 (pt) |
EP (1) | EP2993792B1 (pt) |
JP (1) | JP6229900B2 (pt) |
CN (1) | CN105164925B (pt) |
AU (1) | AU2014260826C1 (pt) |
BR (1) | BR112015027135B1 (pt) |
CA (1) | CA2909305C (pt) |
HU (1) | HUE059575T2 (pt) |
MX (1) | MX354314B (pt) |
RU (1) | RU2656723C2 (pt) |
WO (1) | WO2014178297A1 (pt) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014178296A1 (ja) * | 2013-05-02 | 2014-11-06 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
BR112015027145B1 (pt) * | 2013-05-02 | 2022-05-31 | Sony Corporation | Dispositivo e método de processamento de dados |
KR102240745B1 (ko) * | 2015-01-20 | 2021-04-16 | 한국전자통신연구원 | 길이가 64800이며, 부호율이 4/15인 ldpc 부호어 및 qpsk를 위한 비트 인터리버 및 이를 이용한 비트 인터리빙 방법 |
KR102240748B1 (ko) * | 2015-01-20 | 2021-04-16 | 한국전자통신연구원 | 길이가 64800이며, 부호율이 3/15인 ldpc 부호어 및 qpsk를 위한 비트 인터리버 및 이를 이용한 비트 인터리빙 방법 |
KR102240736B1 (ko) * | 2015-01-27 | 2021-04-16 | 한국전자통신연구원 | 길이가 64800이며, 부호율이 3/15인 ldpc 부호어 및 64-심볼 맵핑을 위한 비트 인터리버 및 이를 이용한 비트 인터리빙 방법 |
US10855416B2 (en) * | 2017-11-16 | 2020-12-01 | Mediatek Inc. | Segmentation of control payload for channel encoding |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1224226C (zh) * | 2001-06-09 | 2005-10-19 | 三星电子株式会社 | 通信系统中重新排列码字序列的方法和设备 |
JP3823315B2 (ja) * | 2002-05-07 | 2006-09-20 | ソニー株式会社 | 符号化装置及び符号化方法、並びに復号装置及び復号方法 |
JP4224777B2 (ja) | 2003-05-13 | 2009-02-18 | ソニー株式会社 | 復号方法および復号装置、並びにプログラム |
KR100809619B1 (ko) * | 2003-08-26 | 2008-03-05 | 삼성전자주식회사 | 이동 통신 시스템에서 블록 저밀도 패러티 검사 부호부호화/복호 장치 및 방법 |
CN100452928C (zh) * | 2003-12-25 | 2009-01-14 | 西安电子科技大学 | 混合递归网格空时码的编码方法 |
US8453030B2 (en) * | 2006-10-26 | 2013-05-28 | Qualcomm Incorporated | Coding schemes for wireless communication transmissions |
US8145971B2 (en) * | 2006-11-29 | 2012-03-27 | Mediatek Inc. | Data processing systems and methods for processing digital data with low density parity check matrix |
US8234538B2 (en) * | 2007-04-26 | 2012-07-31 | Nec Laboratories America, Inc. | Ultra high-speed optical transmission based on LDPC-coded modulation and coherent detection for all-optical network |
TWI410055B (zh) * | 2007-11-26 | 2013-09-21 | Sony Corp | Data processing device, data processing method and program product for performing data processing method on computer |
US8429486B2 (en) * | 2007-12-13 | 2013-04-23 | Nec Corporation | Decoding device, data storage device, data communication system, and decoding method |
ITTO20080472A1 (it) | 2008-06-16 | 2009-12-17 | Rai Radiotelevisione Italiana Spa | Metodo di elaborazione di segnali digitali e sistema di trasmissione e ricezione che implementa detto metodo |
JP5320964B2 (ja) * | 2008-10-08 | 2013-10-23 | ソニー株式会社 | サイクリックシフト装置、サイクリックシフト方法、ldpc復号装置、テレビジョン受像機、及び、受信システム |
JP5542580B2 (ja) * | 2010-08-25 | 2014-07-09 | 日本放送協会 | 送信装置及び受信装置 |
JP5648852B2 (ja) * | 2011-05-27 | 2015-01-07 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
JP5664919B2 (ja) * | 2011-06-15 | 2015-02-04 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
EP2536030A1 (en) * | 2011-06-16 | 2012-12-19 | Panasonic Corporation | Bit permutation patterns for BICM with LDPC codes and QAM constellations |
EP2560311A1 (en) | 2011-08-17 | 2013-02-20 | Panasonic Corporation | Cyclic-block permutations for spatial multiplexing with quasi-cyclic LDPC codes |
EP2993794B1 (en) * | 2013-05-02 | 2022-04-06 | Sony Group Corporation | Ldpc coded modulation in combination with 8psk and 16apsk |
BR112015027145B1 (pt) * | 2013-05-02 | 2022-05-31 | Sony Corporation | Dispositivo e método de processamento de dados |
WO2014178296A1 (ja) | 2013-05-02 | 2014-11-06 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
-
2014
- 2014-04-21 HU HUE14791625A patent/HUE059575T2/hu unknown
- 2014-04-21 MX MX2015014876A patent/MX354314B/es active IP Right Grant
- 2014-04-21 CA CA2909305A patent/CA2909305C/en active Active
- 2014-04-21 EP EP14791625.8A patent/EP2993792B1/en active Active
- 2014-04-21 AU AU2014260826A patent/AU2014260826C1/en active Active
- 2014-04-21 BR BR112015027135-9A patent/BR112015027135B1/pt active IP Right Grant
- 2014-04-21 US US14/782,542 patent/US9806742B2/en active Active
- 2014-04-21 JP JP2015514811A patent/JP6229900B2/ja active Active
- 2014-04-21 CN CN201480023817.9A patent/CN105164925B/zh active Active
- 2014-04-21 RU RU2015145972A patent/RU2656723C2/ru active
- 2014-04-21 WO PCT/JP2014/061153 patent/WO2014178297A1/ja active Application Filing
Also Published As
Publication number | Publication date |
---|---|
CN105164925A (zh) | 2015-12-16 |
MX2015014876A (es) | 2016-03-07 |
JPWO2014178297A1 (ja) | 2017-02-23 |
AU2014260826C1 (en) | 2022-07-07 |
AU2014260826B2 (en) | 2018-03-29 |
CA2909305A1 (en) | 2014-11-06 |
RU2656723C2 (ru) | 2018-06-06 |
EP2993792B1 (en) | 2022-06-22 |
RU2015145972A3 (pt) | 2018-03-21 |
CN105164925B (zh) | 2019-04-23 |
JP6229900B2 (ja) | 2017-11-22 |
EP2993792A1 (en) | 2016-03-09 |
HUE059575T2 (hu) | 2022-12-28 |
BR112015027135B1 (pt) | 2022-02-15 |
CA2909305C (en) | 2022-07-19 |
RU2015145972A (ru) | 2017-05-02 |
EP2993792A4 (en) | 2017-04-19 |
AU2014260826A1 (en) | 2015-11-12 |
US20160049960A1 (en) | 2016-02-18 |
WO2014178297A1 (ja) | 2014-11-06 |
US9806742B2 (en) | 2017-10-31 |
MX354314B (es) | 2018-02-26 |
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