BR112013004233A2 - circuito integrado incluindo um analisador de lógica programável com capacidades aprimoradas de análise e depuração e um método para o mesmo - Google Patents

circuito integrado incluindo um analisador de lógica programável com capacidades aprimoradas de análise e depuração e um método para o mesmo

Info

Publication number
BR112013004233A2
BR112013004233A2 BR112013004233A BR112013004233A BR112013004233A2 BR 112013004233 A2 BR112013004233 A2 BR 112013004233A2 BR 112013004233 A BR112013004233 A BR 112013004233A BR 112013004233 A BR112013004233 A BR 112013004233A BR 112013004233 A2 BR112013004233 A2 BR 112013004233A2
Authority
BR
Brazil
Prior art keywords
integrated circuit
logic analyzer
trigger
trigger condition
enhanced analysis
Prior art date
Application number
BR112013004233A
Other languages
English (en)
Other versions
BR112013004233B1 (pt
Inventor
James Ray Bailey
Original Assignee
Lexmark Int Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lexmark Int Inc filed Critical Lexmark Int Inc
Publication of BR112013004233A2 publication Critical patent/BR112013004233A2/pt
Publication of BR112013004233B1 publication Critical patent/BR112013004233B1/pt

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing
    • G06F11/263Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3177Testing of logic operation, e.g. by logic analysers
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31705Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2294Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by remote test

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Debugging And Monitoring (AREA)
  • Logic Circuits (AREA)

Abstract

circuito integrado incluindo um analisador de lógica programável com capacidades aprimoradas de análise e depuração e um método para o mesmo. trata-se de um circuito integrado que inclui um analisador de lógica com capacidades aprimoradas de análise e depuração e um método para o mesmo. em uma modalidade da presente invenção, um analisador de lógica embutido (ela) recebe uma pluralidade de sinais a partir de uma pluralidade de barramentos dentro de um circuito integrado (ic). o ela inclui um módulo de interconexão para selecionar um sinal de disparo e/ou um sinal amostrado a partir da pluralidade de sinais recebidos. um módulo de disparo ajusta pelo menos uma condição de disparo e detecta se o sinal de disparo satisfaz a pelo menos uma condição de disparo. quando a condição de disparo for satisfeita, um módulo de saída realiza pelo menos uma tarefa com base em pelo menos uma condição de disparo satisfeita. se um processo de amostragem for iniciado pelo módulo de saída, a pluralidade de sinais amostrados é amostrada e pode ser armazenada em uma memória. a capacidade do módulo de saída realizar múltiplas tarefas definidas pelo usuário aumenta a capacidade de deputação do ela e o torna mais versátil.
BR112013004233-8A 2010-09-08 2011-09-08 Circuito integrado incluindo um analisador de lógica programável configurável para análise e depuração BR112013004233B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/877,819 US8914681B2 (en) 2009-08-18 2010-09-08 Integrated circuit including a programmable logic analyzer with enhanced analyzing and debugging capabilities and a method therefor
US12/877.819 2010-09-08
PCT/US2011/050755 WO2012033871A1 (en) 2010-09-08 2011-09-08 An integrated circuit including a programmable logic analyzer with enhanced analyzing and debugging capabilities and a method therefor

Publications (2)

Publication Number Publication Date
BR112013004233A2 true BR112013004233A2 (pt) 2016-07-05
BR112013004233B1 BR112013004233B1 (pt) 2020-09-29

Family

ID=45810961

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112013004233-8A BR112013004233B1 (pt) 2010-09-08 2011-09-08 Circuito integrado incluindo um analisador de lógica programável configurável para análise e depuração

Country Status (11)

Country Link
US (2) US8914681B2 (pt)
EP (1) EP2614381B1 (pt)
KR (1) KR101918195B1 (pt)
CN (1) CN103140769B (pt)
AU (1) AU2011299256B2 (pt)
BR (1) BR112013004233B1 (pt)
CA (1) CA2807125C (pt)
HK (1) HK1187411A1 (pt)
RU (1) RU2598908C2 (pt)
SG (1) SG187693A1 (pt)
WO (1) WO2012033871A1 (pt)

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US9170901B2 (en) 2009-08-18 2015-10-27 Lexmark International, Inc. System and method for analyzing an electronics device including a logic analyzer
US8516304B2 (en) * 2009-08-18 2013-08-20 Lexmark International, Inc. Integrated circuit including a programmable logic analyzer with enhanced analyzing and debugging capabilities and a method therefor
US9405651B1 (en) 2013-10-03 2016-08-02 Initial State Technologies, Inc. Apparatus and method for processing log file data
US9405610B1 (en) 2013-10-03 2016-08-02 Initial State Technologies, Inc. Apparatus and method for processing log file data
US9405755B1 (en) 2013-10-03 2016-08-02 Initial State Technologies, Inc. Apparatus and method for processing log file data
GB2526850B (en) * 2014-06-05 2020-11-25 Advanced Risc Mach Ltd Logic analyzer
KR102391385B1 (ko) * 2015-08-13 2022-04-27 삼성전자주식회사 내장형 로직 분석기 및 이를 포함하는 집적 회로
US10860322B2 (en) * 2015-10-30 2020-12-08 Arm Limited Modifying behavior of a data processing unit using rewritable behavior mappings of instructions
US10386410B2 (en) * 2016-12-12 2019-08-20 Samsung Electronics Co., Ltd. Highly flexible performance counter and system debug module
US11688482B2 (en) 2018-08-08 2023-06-27 Numascale As Digital circuit testing and analysis module, system and method thereof
US10816598B1 (en) * 2018-10-01 2020-10-27 Xilinx, Inc. Dynamic debugging of circuits
KR102105031B1 (ko) * 2018-12-31 2020-04-27 주식회사 다빈시스템스 이동통신 장치에서의 타이밍 획득 장치 및 방법
CN113656236B (zh) * 2020-05-12 2024-05-28 大唐移动通信设备有限公司 一种数据处理方法和装置
CN112634801B (zh) * 2021-01-08 2022-06-10 北京集睿致远科技有限公司 一种片内逻辑分析仪及芯片调试方法
US11639962B1 (en) 2021-03-12 2023-05-02 Xilinx, Inc. Scalable scan architecture for multi-circuit block arrays
CN117452190A (zh) * 2023-12-22 2024-01-26 合肥联宝信息技术有限公司 一种信号测试电路、方法及存储介质

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US6286114B1 (en) * 1997-10-27 2001-09-04 Altera Corporation Enhanced embedded logic analyzer
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Also Published As

Publication number Publication date
CN103140769B (zh) 2015-11-25
BR112013004233B1 (pt) 2020-09-29
CA2807125A1 (en) 2012-03-15
EP2614381B1 (en) 2015-11-18
WO2012033871A1 (en) 2012-03-15
CN103140769A (zh) 2013-06-05
RU2598908C2 (ru) 2016-10-10
HK1187411A1 (en) 2014-04-04
EP2614381A1 (en) 2013-07-17
CA2807125C (en) 2018-02-27
US8914681B2 (en) 2014-12-16
RU2013104873A (ru) 2014-10-20
KR101918195B1 (ko) 2018-11-14
EP2614381A4 (en) 2014-02-19
KR20130106355A (ko) 2013-09-27
US20110047423A1 (en) 2011-02-24
SG187693A1 (en) 2013-03-28
AU2011299256A1 (en) 2013-02-21
AU2011299256B2 (en) 2016-02-11
US20160011953A1 (en) 2016-01-14

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Legal Events

Date Code Title Description
B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 08/09/2011, OBSERVADAS AS CONDICOES LEGAIS.