BR0302820A - Troca de mensagens de blocos componentes intradecodificador - Google Patents

Troca de mensagens de blocos componentes intradecodificador

Info

Publication number
BR0302820A
BR0302820A BR0302820-8A BR0302820A BR0302820A BR 0302820 A BR0302820 A BR 0302820A BR 0302820 A BR0302820 A BR 0302820A BR 0302820 A BR0302820 A BR 0302820A
Authority
BR
Brazil
Prior art keywords
error
generator
codeword
magnitude
block
Prior art date
Application number
BR0302820-8A
Other languages
English (en)
Portuguese (pt)
Inventor
Louis Robert Litwin
Didier Velez
Original Assignee
Thomson Licensing Sa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Licensing Sa filed Critical Thomson Licensing Sa
Publication of BR0302820A publication Critical patent/BR0302820A/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1803—Error detection or correction; Testing, e.g. of drop-outs by redundancy in data representation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10268—Improvement or modification of read or write signals bit detection or demodulation methods
    • G11B20/10287—Improvement or modification of read or write signals bit detection or demodulation methods using probabilistic methods, e.g. maximum likelihood detectors
    • G11B20/10296—Improvement or modification of read or write signals bit detection or demodulation methods using probabilistic methods, e.g. maximum likelihood detectors using the Viterbi algorithm
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1555—Pipelined decoder implementations

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing (AREA)
  • Algebra (AREA)
  • General Physics & Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Detection And Correction Of Errors (AREA)
BR0302820-8A 2002-01-23 2003-01-22 Troca de mensagens de blocos componentes intradecodificador BR0302820A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/055,114 US7020826B2 (en) 2002-01-23 2002-01-23 Intra-decoder component block messaging
PCT/US2003/001913 WO2003063363A1 (en) 2002-01-23 2003-01-22 Intra-decoder component block messaging

Publications (1)

Publication Number Publication Date
BR0302820A true BR0302820A (pt) 2004-03-09

Family

ID=21995704

Family Applications (1)

Application Number Title Priority Date Filing Date
BR0302820-8A BR0302820A (pt) 2002-01-23 2003-01-22 Troca de mensagens de blocos componentes intradecodificador

Country Status (9)

Country Link
US (1) US7020826B2 (enExample)
EP (1) EP1468499A4 (enExample)
JP (1) JP2005516458A (enExample)
KR (1) KR20040075952A (enExample)
CN (1) CN1757165A (enExample)
BR (1) BR0302820A (enExample)
MX (1) MXPA04007076A (enExample)
MY (1) MY132105A (enExample)
WO (1) WO2003063363A1 (enExample)

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US7225391B1 (en) * 2002-12-17 2007-05-29 Altera Corporation Method and apparatus for parallel computation of linear block codes
KR100906474B1 (ko) * 2003-01-29 2009-07-08 삼성전자주식회사 저밀도 부가정보 발생용 매트릭스를 이용한 에러 정정방법 및그 장치
US7206993B2 (en) * 2003-03-12 2007-04-17 Matsushita Electric Industrial Co., Ltd. Method and device for decoding Reed-Solomon code or extended Reed-Solomon code
US7693928B2 (en) * 2003-04-08 2010-04-06 Analog Devices, Inc. Galois field linear transformer trellis system
FR2861474B1 (fr) * 2003-10-24 2007-04-27 Atmel Corp Procede et appareil pour une periode de traitement variable dans un circuit integre
US7581155B2 (en) * 2003-12-18 2009-08-25 Electronics And Telecommunications Research Institute Apparatus for FEC supporting transmission of variable-length frames in TDMA system and method of using the same
US8161207B1 (en) * 2006-06-22 2012-04-17 Marvell International Ltd. Common block interface for data and control with handshake protocol
US8312345B1 (en) * 2006-09-29 2012-11-13 Marvell International Ltd. Forward error correcting code encoder apparatus
US20080140740A1 (en) * 2006-12-08 2008-06-12 Agere Systems Inc. Systems and methods for processing data sets in parallel
JP4313391B2 (ja) * 2006-12-13 2009-08-12 株式会社日立コミュニケーションテクノロジー 光集線装置および光加入者装置
US8223628B2 (en) * 2007-01-10 2012-07-17 Lantiq Deutschland Gmbh Data transmission method, transmitter, receiver, transceiver and transmission system
US9686045B2 (en) * 2007-04-04 2017-06-20 Lantiq Beteiligungs-GmbH & Co. KG Data transmission and retransmission
JP4672743B2 (ja) * 2008-03-01 2011-04-20 株式会社東芝 誤り訂正装置および誤り訂正方法
KR101489827B1 (ko) * 2008-03-25 2015-02-04 삼성전자주식회사 낸드 플래시 메모리와 컨트롤러 간의 효율적인 프로토콜을사용하는 반도체 메모리 장치
JP4780158B2 (ja) * 2008-08-26 2011-09-28 ソニー株式会社 符号化装置および方法
JP4823349B2 (ja) 2009-11-11 2011-11-24 パナソニック株式会社 三次元映像復号装置及び三次元映像復号方法
KR101154923B1 (ko) * 2010-12-09 2012-06-14 한국과학기술원 비씨에이치 디코더, 이를 포함하는 메모리 시스템 및 비씨에이치 디코딩 방법
US8885740B2 (en) * 2011-02-04 2014-11-11 Marvell World Trade Ltd. Control mode PHY for WLAN
US8924828B2 (en) * 2012-08-30 2014-12-30 Kabushiki Kaisha Toshiba Memory controller, semiconductor storage device, and memory control method for error correction using Chien search
TWI500038B (zh) * 2012-09-28 2015-09-11 Univ Nat Chiao Tung 記憶體系統之全套平行編碼方法與全套平行解碼方法
CN105024707B (zh) * 2015-07-31 2018-05-11 福建联迪商用设备有限公司 一种rs纠错解码方法
US10181864B2 (en) * 2016-02-26 2019-01-15 Altera Corporation Methods and apparatus for performing reed-solomon encoding
US11750222B1 (en) * 2022-06-29 2023-09-05 Synopsys, Inc. Throughput efficient Reed-Solomon forward error correction decoding

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US4875211A (en) 1986-12-10 1989-10-17 Matsushita Electric Industrial Co., Ltd. Galois field arithmetic logic unit
US5099482A (en) * 1989-08-30 1992-03-24 Idaho Research Foundation, Inc. Apparatus for detecting uncorrectable error patterns when using Euclid's algorithm to decode Reed-Solomon (BCH) codes
JPH04315332A (ja) 1991-04-15 1992-11-06 Hitachi Ltd 誤り訂正装置
US5373511A (en) 1992-05-04 1994-12-13 Motorola, Inc. Method for decoding a reed solomon encoded signal with inner code and apparatus for doing same
JP3255386B2 (ja) 1993-12-27 2002-02-12 キヤノン株式会社 誤り訂正符号の復号器
JP3328093B2 (ja) 1994-07-12 2002-09-24 三菱電機株式会社 エラー訂正装置
JP3310185B2 (ja) 1996-11-21 2002-07-29 松下電器産業株式会社 誤り訂正装置
US5905740A (en) * 1997-04-08 1999-05-18 Seagate Technology, Inc. Apparatus and method for error correction
JP3850511B2 (ja) 1997-05-07 2006-11-29 日本テキサス・インスツルメンツ株式会社 リードソロモン復号装置
JPH1131977A (ja) 1997-07-10 1999-02-02 Sony Corp 誤り訂正符号演算器
US6154868A (en) * 1997-07-18 2000-11-28 International Business Machines Corporation Method and means for computationally efficient on-the-fly error correction in linear cyclic codes using ultra-fast error location
US6061826A (en) 1997-07-29 2000-05-09 Philips Electronics North America Corp. Hardware-optimized reed-solomon decoder for large data blocks
US6058500A (en) 1998-01-20 2000-05-02 3Com Corporation High-speed syndrome calculation
US6415413B1 (en) * 1998-06-18 2002-07-02 Globespanvirata, Inc. Configurable Reed-Solomon controller and method
US6347389B1 (en) * 1999-03-23 2002-02-12 Storage Technology Corporation Pipelined high speed reed-solomon error/erasure decoder
US6374383B1 (en) 1999-06-07 2002-04-16 Maxtor Corporation Determining error locations using error correction codes
US6487692B1 (en) * 1999-12-21 2002-11-26 Lsi Logic Corporation Reed-Solomon decoder
US6735737B2 (en) * 2000-02-18 2004-05-11 Texas Instruments Incorporated Error correction structures and methods

Also Published As

Publication number Publication date
KR20040075952A (ko) 2004-08-30
MY132105A (en) 2007-09-28
JP2005516458A (ja) 2005-06-02
WO2003063363A1 (en) 2003-07-31
US20030140301A1 (en) 2003-07-24
CN1757165A (zh) 2006-04-05
US7020826B2 (en) 2006-03-28
MXPA04007076A (es) 2004-10-29
EP1468499A4 (en) 2005-12-14
EP1468499A1 (en) 2004-10-20

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Legal Events

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B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

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B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: NAO APRESENTADA A GUIA DE CUMPRIMENTO DE EXIGENCIA. REFERENTE AS 7A, 8A E 9A ANUIDADES.