KR20040075952A - 인트라-디코더 컴포넌트 블록 메시징 - Google Patents
인트라-디코더 컴포넌트 블록 메시징 Download PDFInfo
- Publication number
- KR20040075952A KR20040075952A KR10-2004-7011352A KR20047011352A KR20040075952A KR 20040075952 A KR20040075952 A KR 20040075952A KR 20047011352 A KR20047011352 A KR 20047011352A KR 20040075952 A KR20040075952 A KR 20040075952A
- Authority
- KR
- South Korea
- Prior art keywords
- error
- block
- code word
- polynomial
- decoder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
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- 208000011580 syndromic disease Diseases 0.000 claims abstract description 63
- 238000000034 method Methods 0.000 claims abstract description 62
- 238000012937 correction Methods 0.000 claims abstract description 59
- 230000004044 response Effects 0.000 claims abstract description 5
- 238000004422 calculation algorithm Methods 0.000 claims description 31
- 238000001514 detection method Methods 0.000 claims description 25
- 230000005540 biological transmission Effects 0.000 claims description 13
- 230000000737 periodic effect Effects 0.000 claims description 12
- 230000009849 deactivation Effects 0.000 claims description 4
- 239000013598 vector Substances 0.000 abstract description 46
- 230000008569 process Effects 0.000 abstract description 28
- 238000004364 calculation method Methods 0.000 abstract description 9
- 230000009977 dual effect Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 23
- 238000012545 processing Methods 0.000 description 20
- 230000006870 function Effects 0.000 description 9
- 230000002441 reversible effect Effects 0.000 description 9
- 238000004891 communication Methods 0.000 description 8
- 238000013461 design Methods 0.000 description 7
- 230000008901 benefit Effects 0.000 description 5
- 238000010845 search algorithm Methods 0.000 description 3
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- 238000010606 normalization Methods 0.000 description 2
- 101150012579 ADSL gene Proteins 0.000 description 1
- 102100020775 Adenylosuccinate lyase Human genes 0.000 description 1
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- 230000008859 change Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000002068 genetic effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012804 iterative process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1803—Error detection or correction; Testing, e.g. of drop-outs by redundancy in data representation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10268—Improvement or modification of read or write signals bit detection or demodulation methods
- G11B20/10287—Improvement or modification of read or write signals bit detection or demodulation methods using probabilistic methods, e.g. maximum likelihood detectors
- G11B20/10296—Improvement or modification of read or write signals bit detection or demodulation methods using probabilistic methods, e.g. maximum likelihood detectors using the Viterbi algorithm
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/1515—Reed-Solomon codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/1555—Pipelined decoder implementations
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Signal Processing (AREA)
- Algebra (AREA)
- General Physics & Mathematics (AREA)
- Pure & Applied Mathematics (AREA)
- Error Detection And Correction (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Detection And Correction Of Errors (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/055,114 US7020826B2 (en) | 2002-01-23 | 2002-01-23 | Intra-decoder component block messaging |
| US10/055,114 | 2002-01-23 | ||
| PCT/US2003/001913 WO2003063363A1 (en) | 2002-01-23 | 2003-01-22 | Intra-decoder component block messaging |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20040075952A true KR20040075952A (ko) | 2004-08-30 |
Family
ID=21995704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2004-7011352A Ceased KR20040075952A (ko) | 2002-01-23 | 2003-01-22 | 인트라-디코더 컴포넌트 블록 메시징 |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US7020826B2 (enExample) |
| EP (1) | EP1468499A4 (enExample) |
| JP (1) | JP2005516458A (enExample) |
| KR (1) | KR20040075952A (enExample) |
| CN (1) | CN1757165A (enExample) |
| BR (1) | BR0302820A (enExample) |
| MX (1) | MXPA04007076A (enExample) |
| MY (1) | MY132105A (enExample) |
| WO (1) | WO2003063363A1 (enExample) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101154923B1 (ko) * | 2010-12-09 | 2012-06-14 | 한국과학기술원 | 비씨에이치 디코더, 이를 포함하는 메모리 시스템 및 비씨에이치 디코딩 방법 |
| KR101489827B1 (ko) * | 2008-03-25 | 2015-02-04 | 삼성전자주식회사 | 낸드 플래시 메모리와 컨트롤러 간의 효율적인 프로토콜을사용하는 반도체 메모리 장치 |
Families Citing this family (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7225391B1 (en) * | 2002-12-17 | 2007-05-29 | Altera Corporation | Method and apparatus for parallel computation of linear block codes |
| KR100906474B1 (ko) * | 2003-01-29 | 2009-07-08 | 삼성전자주식회사 | 저밀도 부가정보 발생용 매트릭스를 이용한 에러 정정방법 및그 장치 |
| US7206993B2 (en) * | 2003-03-12 | 2007-04-17 | Matsushita Electric Industrial Co., Ltd. | Method and device for decoding Reed-Solomon code or extended Reed-Solomon code |
| US7693928B2 (en) * | 2003-04-08 | 2010-04-06 | Analog Devices, Inc. | Galois field linear transformer trellis system |
| FR2861474B1 (fr) * | 2003-10-24 | 2007-04-27 | Atmel Corp | Procede et appareil pour une periode de traitement variable dans un circuit integre |
| US7581155B2 (en) * | 2003-12-18 | 2009-08-25 | Electronics And Telecommunications Research Institute | Apparatus for FEC supporting transmission of variable-length frames in TDMA system and method of using the same |
| US8161207B1 (en) * | 2006-06-22 | 2012-04-17 | Marvell International Ltd. | Common block interface for data and control with handshake protocol |
| US8312345B1 (en) * | 2006-09-29 | 2012-11-13 | Marvell International Ltd. | Forward error correcting code encoder apparatus |
| US20080140740A1 (en) * | 2006-12-08 | 2008-06-12 | Agere Systems Inc. | Systems and methods for processing data sets in parallel |
| JP4313391B2 (ja) * | 2006-12-13 | 2009-08-12 | 株式会社日立コミュニケーションテクノロジー | 光集線装置および光加入者装置 |
| US8223628B2 (en) * | 2007-01-10 | 2012-07-17 | Lantiq Deutschland Gmbh | Data transmission method, transmitter, receiver, transceiver and transmission system |
| US9686045B2 (en) * | 2007-04-04 | 2017-06-20 | Lantiq Beteiligungs-GmbH & Co. KG | Data transmission and retransmission |
| JP4672743B2 (ja) * | 2008-03-01 | 2011-04-20 | 株式会社東芝 | 誤り訂正装置および誤り訂正方法 |
| JP4780158B2 (ja) * | 2008-08-26 | 2011-09-28 | ソニー株式会社 | 符号化装置および方法 |
| JP4823349B2 (ja) | 2009-11-11 | 2011-11-24 | パナソニック株式会社 | 三次元映像復号装置及び三次元映像復号方法 |
| US8885740B2 (en) * | 2011-02-04 | 2014-11-11 | Marvell World Trade Ltd. | Control mode PHY for WLAN |
| US8924828B2 (en) * | 2012-08-30 | 2014-12-30 | Kabushiki Kaisha Toshiba | Memory controller, semiconductor storage device, and memory control method for error correction using Chien search |
| TWI500038B (zh) * | 2012-09-28 | 2015-09-11 | Univ Nat Chiao Tung | 記憶體系統之全套平行編碼方法與全套平行解碼方法 |
| CN105024707B (zh) * | 2015-07-31 | 2018-05-11 | 福建联迪商用设备有限公司 | 一种rs纠错解码方法 |
| US10181864B2 (en) * | 2016-02-26 | 2019-01-15 | Altera Corporation | Methods and apparatus for performing reed-solomon encoding |
| US11750222B1 (en) * | 2022-06-29 | 2023-09-05 | Synopsys, Inc. | Throughput efficient Reed-Solomon forward error correction decoding |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4875211A (en) | 1986-12-10 | 1989-10-17 | Matsushita Electric Industrial Co., Ltd. | Galois field arithmetic logic unit |
| US5099482A (en) * | 1989-08-30 | 1992-03-24 | Idaho Research Foundation, Inc. | Apparatus for detecting uncorrectable error patterns when using Euclid's algorithm to decode Reed-Solomon (BCH) codes |
| JPH04315332A (ja) | 1991-04-15 | 1992-11-06 | Hitachi Ltd | 誤り訂正装置 |
| US5373511A (en) | 1992-05-04 | 1994-12-13 | Motorola, Inc. | Method for decoding a reed solomon encoded signal with inner code and apparatus for doing same |
| JP3255386B2 (ja) | 1993-12-27 | 2002-02-12 | キヤノン株式会社 | 誤り訂正符号の復号器 |
| JP3328093B2 (ja) | 1994-07-12 | 2002-09-24 | 三菱電機株式会社 | エラー訂正装置 |
| JP3310185B2 (ja) | 1996-11-21 | 2002-07-29 | 松下電器産業株式会社 | 誤り訂正装置 |
| US5905740A (en) * | 1997-04-08 | 1999-05-18 | Seagate Technology, Inc. | Apparatus and method for error correction |
| JP3850511B2 (ja) | 1997-05-07 | 2006-11-29 | 日本テキサス・インスツルメンツ株式会社 | リードソロモン復号装置 |
| JPH1131977A (ja) | 1997-07-10 | 1999-02-02 | Sony Corp | 誤り訂正符号演算器 |
| US6154868A (en) * | 1997-07-18 | 2000-11-28 | International Business Machines Corporation | Method and means for computationally efficient on-the-fly error correction in linear cyclic codes using ultra-fast error location |
| US6061826A (en) | 1997-07-29 | 2000-05-09 | Philips Electronics North America Corp. | Hardware-optimized reed-solomon decoder for large data blocks |
| US6058500A (en) | 1998-01-20 | 2000-05-02 | 3Com Corporation | High-speed syndrome calculation |
| US6415413B1 (en) * | 1998-06-18 | 2002-07-02 | Globespanvirata, Inc. | Configurable Reed-Solomon controller and method |
| US6347389B1 (en) * | 1999-03-23 | 2002-02-12 | Storage Technology Corporation | Pipelined high speed reed-solomon error/erasure decoder |
| US6374383B1 (en) | 1999-06-07 | 2002-04-16 | Maxtor Corporation | Determining error locations using error correction codes |
| US6487692B1 (en) * | 1999-12-21 | 2002-11-26 | Lsi Logic Corporation | Reed-Solomon decoder |
| US6735737B2 (en) * | 2000-02-18 | 2004-05-11 | Texas Instruments Incorporated | Error correction structures and methods |
-
2002
- 2002-01-23 US US10/055,114 patent/US7020826B2/en not_active Expired - Fee Related
-
2003
- 2003-01-22 KR KR10-2004-7011352A patent/KR20040075952A/ko not_active Ceased
- 2003-01-22 WO PCT/US2003/001913 patent/WO2003063363A1/en not_active Ceased
- 2003-01-22 MY MYPI20030217A patent/MY132105A/en unknown
- 2003-01-22 BR BR0302820-8A patent/BR0302820A/pt not_active IP Right Cessation
- 2003-01-22 MX MXPA04007076A patent/MXPA04007076A/es active IP Right Grant
- 2003-01-22 CN CNA038026554A patent/CN1757165A/zh active Pending
- 2003-01-22 JP JP2003563105A patent/JP2005516458A/ja not_active Withdrawn
- 2003-01-22 EP EP03732044A patent/EP1468499A4/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101489827B1 (ko) * | 2008-03-25 | 2015-02-04 | 삼성전자주식회사 | 낸드 플래시 메모리와 컨트롤러 간의 효율적인 프로토콜을사용하는 반도체 메모리 장치 |
| KR101154923B1 (ko) * | 2010-12-09 | 2012-06-14 | 한국과학기술원 | 비씨에이치 디코더, 이를 포함하는 메모리 시스템 및 비씨에이치 디코딩 방법 |
Also Published As
| Publication number | Publication date |
|---|---|
| MY132105A (en) | 2007-09-28 |
| JP2005516458A (ja) | 2005-06-02 |
| WO2003063363A1 (en) | 2003-07-31 |
| US20030140301A1 (en) | 2003-07-24 |
| CN1757165A (zh) | 2006-04-05 |
| US7020826B2 (en) | 2006-03-28 |
| MXPA04007076A (es) | 2004-10-29 |
| EP1468499A4 (en) | 2005-12-14 |
| BR0302820A (pt) | 2004-03-09 |
| EP1468499A1 (en) | 2004-10-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0105 | International application |
Patent event date: 20040722 Patent event code: PA01051R01D Comment text: International Patent Application |
|
| PG1501 | Laying open of application | ||
| A201 | Request for examination | ||
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 20080122 Comment text: Request for Examination of Application |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20090630 Patent event code: PE09021S01D |
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| E601 | Decision to refuse application | ||
| PE0601 | Decision on rejection of patent |
Patent event date: 20091202 Comment text: Decision to Refuse Application Patent event code: PE06012S01D Patent event date: 20090630 Comment text: Notification of reason for refusal Patent event code: PE06011S01I |