DE60004057D1 - ERROR CORRECTION CIRCUIT AND METHOD IN A STORAGE DEVICE - Google Patents

ERROR CORRECTION CIRCUIT AND METHOD IN A STORAGE DEVICE

Info

Publication number
DE60004057D1
DE60004057D1 DE60004057T DE60004057T DE60004057D1 DE 60004057 D1 DE60004057 D1 DE 60004057D1 DE 60004057 T DE60004057 T DE 60004057T DE 60004057 T DE60004057 T DE 60004057T DE 60004057 D1 DE60004057 D1 DE 60004057D1
Authority
DE
Germany
Prior art keywords
error correction
correction circuit
storage
error
improving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60004057T
Other languages
English (en)
Inventor
Monroe Walters
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US09/314,574 priority Critical patent/US6584594B1/en
Priority to US09/314,575 priority patent/US6438726B1/en
Priority to US09/314,576 priority patent/US6360347B1/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to PCT/US2000/013385 priority patent/WO2000070459A1/en
Application granted granted Critical
Publication of DE60004057D1 publication Critical patent/DE60004057D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/18Error detection or correction; Testing, e.g. of drop-outs
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
DE60004057T 1999-05-18 2000-05-16 ERROR CORRECTION CIRCUIT AND METHOD IN A STORAGE DEVICE Expired - Lifetime DE60004057D1 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US09/314,574 US6584594B1 (en) 1999-05-18 1999-05-18 Data pre-reading and error correction circuit for a memory device
US09/314,575 US6438726B1 (en) 1999-05-18 1999-05-18 Method of dual use of non-volatile memory for error correction
US09/314,576 US6360347B1 (en) 1999-05-18 1999-05-18 Error correction method for a memory device
PCT/US2000/013385 WO2000070459A1 (en) 1999-05-18 2000-05-16 Error correction circuit and method for a memory device

Publications (1)

Publication Number Publication Date
DE60004057D1 true DE60004057D1 (de) 2003-08-28

Family

ID=27405731

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60004057T Expired - Lifetime DE60004057D1 (de) 1999-05-18 2000-05-16 ERROR CORRECTION CIRCUIT AND METHOD IN A STORAGE DEVICE

Country Status (7)

Country Link
EP (1) EP1192544B1 (de)
JP (1) JP2002544622A (de)
KR (1) KR20020007414A (de)
AT (1) AT245835T (de)
DE (1) DE60004057D1 (de)
TW (1) TW479223B (de)
WO (1) WO2000070459A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100634414B1 (ko) 2004-09-06 2006-10-16 삼성전자주식회사 에러 검출용 패러티 발생기를 구비한 낸드 플래시 메모리 장치 및 그것의 에러 검출 방법
CN101558394B (zh) * 2006-09-06 2013-06-19 极速决件有限公司 用来保护内容的方法、系统和介质
US8135935B2 (en) * 2007-03-20 2012-03-13 Advanced Micro Devices, Inc. ECC implementation in non-ECC components
JP2012155541A (ja) 2011-01-26 2012-08-16 Toshiba Corp データ記憶装置、メモリ制御装置及びメモリ制御方法
EP2608036A1 (de) 2011-12-22 2013-06-26 Thomson Licensing Verfahren und System zum Verwalten der Fehlererkennung und -korrektur
KR101361238B1 (ko) * 2012-06-05 2014-02-25 한국과학기술원 간섭 채널 환경에서의 오류 정정 방법 및 회로, 이를 이용한 플래시 메모리 장치

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2830308B2 (ja) * 1990-02-26 1998-12-02 日本電気株式会社 情報処理装置
JP3272903B2 (ja) * 1995-03-16 2002-04-08 株式会社東芝 誤り訂正検出回路と半導体記憶装置

Also Published As

Publication number Publication date
AT245835T (de) 2003-08-15
JP2002544622A (ja) 2002-12-24
EP1192544B1 (de) 2003-07-23
TW479223B (en) 2002-03-11
KR20020007414A (ko) 2002-01-26
EP1192544A1 (de) 2002-04-03
WO2000070459A1 (en) 2000-11-23

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Legal Events

Date Code Title Description
8332 No legal effect for de