BR0212659A - arquitetura baseada em edram - Google Patents

arquitetura baseada em edram

Info

Publication number
BR0212659A
BR0212659A BRPI0212659-1A BR0212659A BR0212659A BR 0212659 A BR0212659 A BR 0212659A BR 0212659 A BR0212659 A BR 0212659A BR 0212659 A BR0212659 A BR 0212659A
Authority
BR
Brazil
Prior art keywords
memory
elements
based architecture
renewal
edram
Prior art date
Application number
BRPI0212659-1A
Other languages
English (en)
Portuguese (pt)
Inventor
Haitao Zhang
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR0212659A publication Critical patent/BR0212659A/pt

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40622Partial refresh of memory arrays
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Storage Device Security (AREA)
  • Mobile Radio Communication Systems (AREA)
BRPI0212659-1A 2001-09-20 2002-09-19 arquitetura baseada em edram BR0212659A (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US32401301P 2001-09-20 2001-09-20
US10/242,878 US20030053361A1 (en) 2001-09-20 2002-09-11 EDRAM based architecture
PCT/US2002/030000 WO2003025947A2 (en) 2001-09-20 2002-09-19 Edram based architecture

Publications (1)

Publication Number Publication Date
BR0212659A true BR0212659A (pt) 2007-11-06

Family

ID=26935419

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0212659-1A BR0212659A (pt) 2001-09-20 2002-09-19 arquitetura baseada em edram

Country Status (6)

Country Link
US (1) US20030053361A1 (enExample)
JP (1) JP2005528717A (enExample)
BR (1) BR0212659A (enExample)
CA (1) CA2461018A1 (enExample)
RU (1) RU2004111785A (enExample)
WO (1) WO2003025947A2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7590021B2 (en) * 2007-07-26 2009-09-15 Qualcomm Incorporated System and method to reduce dynamic RAM power consumption via the use of valid data indicators
US20090144507A1 (en) * 2007-12-04 2009-06-04 International Business Machines Corporation APPARATUS AND METHOD FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS
US8024513B2 (en) * 2007-12-04 2011-09-20 International Business Machines Corporation Method and system for implementing dynamic refresh protocols for DRAM based cache
US7882302B2 (en) * 2007-12-04 2011-02-01 International Business Machines Corporation Method and system for implementing prioritized refresh of DRAM based cache
US7962695B2 (en) * 2007-12-04 2011-06-14 International Business Machines Corporation Method and system for integrating SRAM and DRAM architecture in set associative cache
US20090144504A1 (en) * 2007-12-04 2009-06-04 International Business Machines Corporation STRUCTURE FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS
US8108609B2 (en) * 2007-12-04 2012-01-31 International Business Machines Corporation Structure for implementing dynamic refresh protocols for DRAM based cache
CN103559142B (zh) * 2013-11-05 2017-03-08 中国科学院声学研究所 动态随机访问存储器的刷新方法
US10811076B1 (en) * 2019-06-29 2020-10-20 Intel Corporation Battery life based on inhibited memory refreshes

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5148546A (en) * 1991-04-22 1992-09-15 Blodgett Greg A Method and system for minimizing power demands on portable computers and the like by refreshing selected dram cells
IL121044A (en) * 1996-07-15 2000-09-28 Motorola Inc Dynamic memory device

Also Published As

Publication number Publication date
JP2005528717A (ja) 2005-09-22
WO2003025947A3 (en) 2003-11-13
CA2461018A1 (en) 2003-03-27
RU2004111785A (ru) 2005-10-20
US20030053361A1 (en) 2003-03-20
WO2003025947A2 (en) 2003-03-27

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Legal Events

Date Code Title Description
B08F Application fees: application dismissed [chapter 8.6 patent gazette]

Free format text: REFERENTE A 7A ANUIDADE.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 DA RPI 2029 DE 24/11/2009.