ATE390667T1 - Verbessertes speichermanagement für echtzeitanwendungen - Google Patents

Verbessertes speichermanagement für echtzeitanwendungen

Info

Publication number
ATE390667T1
ATE390667T1 AT03812611T AT03812611T ATE390667T1 AT E390667 T1 ATE390667 T1 AT E390667T1 AT 03812611 T AT03812611 T AT 03812611T AT 03812611 T AT03812611 T AT 03812611T AT E390667 T1 ATE390667 T1 AT E390667T1
Authority
AT
Austria
Prior art keywords
memory management
real
address translation
time applications
improved memory
Prior art date
Application number
AT03812611T
Other languages
English (en)
Inventor
Michael Day
Harm Hofstee
Charles Johns
James Kahle
Thuong Truong
David Shippy
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE390667T1 publication Critical patent/ATE390667T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)
  • Exchange Systems With Centralized Control (AREA)
AT03812611T 2002-12-12 2003-11-21 Verbessertes speichermanagement für echtzeitanwendungen ATE390667T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/318,541 US7103748B2 (en) 2002-12-12 2002-12-12 Memory management for real-time applications

Publications (1)

Publication Number Publication Date
ATE390667T1 true ATE390667T1 (de) 2008-04-15

Family

ID=32506386

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03812611T ATE390667T1 (de) 2002-12-12 2003-11-21 Verbessertes speichermanagement für echtzeitanwendungen

Country Status (11)

Country Link
US (1) US7103748B2 (de)
EP (1) EP1581873B1 (de)
JP (1) JP4129458B2 (de)
KR (1) KR100843536B1 (de)
CN (1) CN100397367C (de)
AT (1) ATE390667T1 (de)
AU (1) AU2003302824A1 (de)
CA (1) CA2505610C (de)
DE (1) DE60320026T2 (de)
IL (1) IL169136A0 (de)
WO (1) WO2004053698A2 (de)

Families Citing this family (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6862027B2 (en) * 2003-06-30 2005-03-01 Microsoft Corp. System and method for parallel execution of data generation tasks
US7355601B2 (en) * 2003-06-30 2008-04-08 International Business Machines Corporation System and method for transfer of data between processors using a locked set, head and tail pointers
JP2005132525A (ja) * 2003-10-29 2005-05-26 Toyota Industries Corp 産業車輌における立席型運転席用背もたれ構造
US7519791B2 (en) * 2004-02-06 2009-04-14 Intel Corporation Address conversion technique in a context switching environment
US7089341B2 (en) * 2004-03-31 2006-08-08 International Business Machines Corporation Method and apparatus for supporting interrupt devices configured for a particular architecture on a different platform
US7362705B2 (en) * 2004-05-13 2008-04-22 International Business Machines Corporation Dynamic load-based credit distribution
JP4233492B2 (ja) * 2004-06-02 2009-03-04 富士通マイクロエレクトロニクス株式会社 アドレス変換装置
US7840757B2 (en) * 2004-07-29 2010-11-23 International Business Machines Corporation Method and apparatus for providing high speed memory for a processing unit
US20060047862A1 (en) * 2004-09-02 2006-03-02 International Business Machines Corporation Automatic hardware data link initialization
US20060045031A1 (en) * 2004-09-02 2006-03-02 International Business Machines Corporation Automatic hardware data link initialization using multiple state machines
US7546401B2 (en) * 2004-09-23 2009-06-09 International Business Machines Corporation Byte to byte alignment of multi-path data
US7475190B2 (en) * 2004-10-08 2009-01-06 International Business Machines Corporation Direct access of cache lock set data without backing memory
US7577794B2 (en) 2004-10-08 2009-08-18 International Business Machines Corporation Low latency coherency protocol for a multi-chip multiprocessor system
US20060080511A1 (en) * 2004-10-08 2006-04-13 International Business Machines Corporation Enhanced bus transactions for efficient support of a remote cache directory copy
US7305524B2 (en) * 2004-10-08 2007-12-04 International Business Machines Corporation Snoop filter directory mechanism in coherency shared memory system
US8332592B2 (en) * 2004-10-08 2012-12-11 International Business Machines Corporation Graphics processor with snoop filter
US7385925B2 (en) * 2004-11-04 2008-06-10 International Business Machines Corporation Data flow control method for simultaneous packet reception
US7260765B2 (en) * 2004-12-17 2007-08-21 International Business Machines Corporation Methods and apparatus for dynamically reconfigurable parallel data error checking
US7499452B2 (en) * 2004-12-28 2009-03-03 International Business Machines Corporation Self-healing link sequence counts within a circular buffer
US20060140122A1 (en) * 2004-12-28 2006-06-29 International Business Machines Corporation Link retry per virtual channel
US20060159023A1 (en) * 2005-01-14 2006-07-20 International Business Machines Corporation CRC error history mechanism
US7275124B2 (en) * 2005-02-24 2007-09-25 International Business Machines Corporation Method and system for controlling forwarding or terminating of a request at a bus interface based on buffer availability
US7275125B2 (en) * 2005-02-24 2007-09-25 International Business Machines Corporation Pipeline bit handling circuit and method for a bus bridge
US20060190655A1 (en) * 2005-02-24 2006-08-24 International Business Machines Corporation Apparatus and method for transaction tag mapping between bus domains
US7194567B2 (en) * 2005-02-24 2007-03-20 International Business Machines Corporation Method and system for ordering requests at a bus interface
US7330925B2 (en) * 2005-02-24 2008-02-12 International Business Machines Corporation Transaction flow control mechanism for a bus bridge
US7234017B2 (en) * 2005-02-24 2007-06-19 International Business Machines Corporation Computer system architecture for a processor connected to a high speed bus transceiver
US7206886B2 (en) * 2005-02-24 2007-04-17 International Business Machines Corporation Data ordering translation between linear and interleaved domains at a bus interface
US7469312B2 (en) * 2005-02-24 2008-12-23 International Business Machines Corporation Computer system bus bridge
US7500062B2 (en) * 2005-11-17 2009-03-03 International Business Machines Corporation Fast path memory read request processing in a multi-level memory architecture
JP2007233615A (ja) * 2006-02-28 2007-09-13 Fujitsu Ltd アドレス変換装置
US7886112B2 (en) * 2006-05-24 2011-02-08 Sony Computer Entertainment Inc. Methods and apparatus for providing simultaneous software/hardware cache fill
US7908439B2 (en) * 2007-06-25 2011-03-15 International Business Machines Corporation Method and apparatus for efficient replacement algorithm for pre-fetcher oriented data cache
US8099579B2 (en) * 2007-07-13 2012-01-17 International Business Machines Corporation System and method for cache-locking mechanism using segment table attributes for replacement class ID determination
US8244979B2 (en) * 2007-07-13 2012-08-14 International Business Machines Corporation System and method for cache-locking mechanism using translation table attributes for replacement class ID determination
US20090049272A1 (en) * 2007-08-13 2009-02-19 International Business Machines Corporation Method for improving the performance of software-managed tlb
US8966219B2 (en) * 2007-10-30 2015-02-24 International Business Machines Corporation Address translation through an intermediate address space
US8108617B2 (en) * 2008-02-08 2012-01-31 International Business Machines Corporation Method to bypass cache levels in a cache coherent system
JP5300407B2 (ja) 2008-10-20 2013-09-25 株式会社東芝 仮想アドレスキャッシュメモリ及び仮想アドレスキャッシュ方法
KR100987332B1 (ko) 2008-11-07 2010-10-18 서울대학교산학협력단 메모리 구조에 따른 메모리 관리 장치
EP2192493A1 (de) 2008-11-28 2010-06-02 ST Wireless SA Verfahren zum Rufen auf Anfrage für eine virtuelle Speicherverwaltung in einem Verarbeitungssystem und entsprechendes Verarbeitungssystem
US8397049B2 (en) * 2009-07-13 2013-03-12 Apple Inc. TLB prefetching
CN102662869B (zh) * 2012-04-01 2015-08-26 龙芯中科技术有限公司 虚拟机中的内存访问方法和装置及查找器
US9003125B2 (en) * 2012-06-14 2015-04-07 International Business Machines Corporation Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable index
US9086980B2 (en) 2012-08-01 2015-07-21 International Business Machines Corporation Data processing, method, device, and system for processing requests in a multi-core system
US9213532B2 (en) 2013-09-26 2015-12-15 Oracle International Corporation Method for ordering text in a binary
US11216361B2 (en) 2016-06-29 2022-01-04 Western Digital Technologies, Inc. Translation lookup and garbage collection optimizations on storage system with paged translation table
US10235287B2 (en) 2016-06-29 2019-03-19 Western Digital Technologies, Inc. Efficient management of paged translation maps in memory and flash
US10229048B2 (en) 2016-06-29 2019-03-12 Western Digital Technologies, Inc. Unified paging scheme for dense and sparse translation tables on flash storage systems
US10353813B2 (en) 2016-06-29 2019-07-16 Western Digital Technologies, Inc. Checkpoint based technique for bootstrapping forward map under constrained memory for flash devices
US10175896B2 (en) 2016-06-29 2019-01-08 Western Digital Technologies, Inc. Incremental snapshot based technique on paged translation systems
US10579522B2 (en) * 2016-09-13 2020-03-03 Andes Technology Corporation Method and device for accessing a cache memory

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4727485A (en) 1986-01-02 1988-02-23 Motorola, Inc. Paged memory management unit which locks translators in translation cache if lock specified in translation table
US5487162A (en) * 1992-02-25 1996-01-23 Matsushita Electric Industrial Co., Ltd. Cache lock information feeding system using an address translator
JP3740195B2 (ja) * 1994-09-09 2006-02-01 株式会社ルネサステクノロジ データ処理装置
US5594886A (en) * 1994-10-23 1997-01-14 Lsi Logic Corporation Pseudo-LRU cache memory replacement method and apparatus utilizing nodes
DE69814703D1 (de) 1997-01-30 2003-06-26 Sgs Thomson Microelectronics Cachespeichersystem für gleichzeitig laufende Prozesse
JP2000200221A (ja) * 1998-10-30 2000-07-18 Nec Corp キャッシュメモリ装置及びその制御方法
US6442664B1 (en) * 1999-06-01 2002-08-27 International Business Machines Corporation Computer memory address translation system
US6430667B1 (en) * 2000-04-13 2002-08-06 International Business Machines Corporation Single-level store computer incorporating process-local address translation data structures
EP1182569B8 (de) 2000-08-21 2011-07-06 Texas Instruments Incorporated TLB-Ver- und Entriegelungsoperation
JP2002140234A (ja) 2000-11-02 2002-05-17 Hitachi Ltd キャッシュ装置
US20030159003A1 (en) * 2001-10-23 2003-08-21 Ip-First, Llc Associative cache memory with replacement way information integrated into directory
US7020748B2 (en) * 2003-01-21 2006-03-28 Sun Microsystems, Inc. Cache replacement policy to mitigate pollution in multicore processors

Also Published As

Publication number Publication date
CA2505610A1 (en) 2004-06-24
KR100843536B1 (ko) 2008-07-04
JP4129458B2 (ja) 2008-08-06
KR20050088077A (ko) 2005-09-01
DE60320026D1 (de) 2008-05-08
US20040117592A1 (en) 2004-06-17
IL169136A0 (en) 2007-07-04
EP1581873B1 (de) 2008-03-26
JP2006515088A (ja) 2006-05-18
CN1820258A (zh) 2006-08-16
DE60320026T2 (de) 2009-05-14
WO2004053698A2 (en) 2004-06-24
US7103748B2 (en) 2006-09-05
CA2505610C (en) 2009-06-23
EP1581873A2 (de) 2005-10-05
AU2003302824A1 (en) 2004-06-30
AU2003302824A8 (en) 2004-06-30
CN100397367C (zh) 2008-06-25
WO2004053698A3 (en) 2006-01-12

Similar Documents

Publication Publication Date Title
ATE390667T1 (de) Verbessertes speichermanagement für echtzeitanwendungen
US10089242B2 (en) Memory management for a hierarchical memory system
US7930515B2 (en) Virtual memory management
US9384134B2 (en) Persistent memory for processor main memory
ATE335334T1 (de) Vlan tabellenverwaltungssystem in hardwarebasierten paketvermittlungsstellen für speichereffizientes auslesen und einschreiben
US8825718B2 (en) Methods and apparatus for marking objects for garbage collection in an object-based memory system
CN105389264B (zh) 存储系统中垃圾收集的方法和系统
EP2472412B1 (de) Ausdrücklich in Regionen eingeteilte Speicherorganisation in einem Netzwerkelement
RU2006107184A (ru) Способ и система для создания, хранения, управления и потребления специфичных культуре данных
CA2538568A1 (en) Data profiling
KR970066887A (ko) 다중 레벨 다이나믹 세트 예측 방법 및 장치
WO2002073415A3 (en) Cache way prediction based on instruction base register
RU2009131695A (ru) Способ и устройство для установки политики кэширования в процессоре
CN105378685A (zh) 数据存储装置和用于给数据存储装置分配数据的方法
JP2002123424A5 (de)
US20040205295A1 (en) Apparatus and method to share a cache memory
US8468297B2 (en) Content addressable memory system
DE60038307D1 (de) Assoziativspeicher zur cachespeicherung
US12093180B2 (en) Tags and data for caches
US10372615B1 (en) Data management for cache memory
CN103077133B (zh) 提供可变长度高速缓存线的高速缓存器控制器及方法
US10236066B2 (en) Method of managing semiconductor memories, corresponding interface, memory and device
WO2020001665A3 (zh) 一种片内缓存及集成芯片
CN110806987A (zh) 一种在静态随机存取存储器上的混合型映象表
CN104636268A (zh) 一种可重构缓存组织结构

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties