CA2461018A1 - Edram based architecture - Google Patents
Edram based architecture Download PDFInfo
- Publication number
- CA2461018A1 CA2461018A1 CA002461018A CA2461018A CA2461018A1 CA 2461018 A1 CA2461018 A1 CA 2461018A1 CA 002461018 A CA002461018 A CA 002461018A CA 2461018 A CA2461018 A CA 2461018A CA 2461018 A1 CA2461018 A1 CA 2461018A1
- Authority
- CA
- Canada
- Prior art keywords
- refresh
- memory
- count
- counter
- elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 230000004044 response Effects 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 4
- 238000004891 communication Methods 0.000 claims description 8
- 230000001413 cellular effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 230000014759 maintenance of location Effects 0.000 description 2
- 238000007726 management method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40622—Partial refresh of memory arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Storage Device Security (AREA)
- Mobile Radio Communication Systems (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US32401301P | 2001-09-20 | 2001-09-20 | |
| US60/324,013 | 2001-09-20 | ||
| US10/242,878 US20030053361A1 (en) | 2001-09-20 | 2002-09-11 | EDRAM based architecture |
| US10/242,878 | 2002-09-11 | ||
| PCT/US2002/030000 WO2003025947A2 (en) | 2001-09-20 | 2002-09-19 | Edram based architecture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2461018A1 true CA2461018A1 (en) | 2003-03-27 |
Family
ID=26935419
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002461018A Abandoned CA2461018A1 (en) | 2001-09-20 | 2002-09-19 | Edram based architecture |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US20030053361A1 (enExample) |
| JP (1) | JP2005528717A (enExample) |
| BR (1) | BR0212659A (enExample) |
| CA (1) | CA2461018A1 (enExample) |
| RU (1) | RU2004111785A (enExample) |
| WO (1) | WO2003025947A2 (enExample) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7590021B2 (en) * | 2007-07-26 | 2009-09-15 | Qualcomm Incorporated | System and method to reduce dynamic RAM power consumption via the use of valid data indicators |
| US7882302B2 (en) * | 2007-12-04 | 2011-02-01 | International Business Machines Corporation | Method and system for implementing prioritized refresh of DRAM based cache |
| US20090144504A1 (en) * | 2007-12-04 | 2009-06-04 | International Business Machines Corporation | STRUCTURE FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS |
| US8024513B2 (en) * | 2007-12-04 | 2011-09-20 | International Business Machines Corporation | Method and system for implementing dynamic refresh protocols for DRAM based cache |
| US8108609B2 (en) * | 2007-12-04 | 2012-01-31 | International Business Machines Corporation | Structure for implementing dynamic refresh protocols for DRAM based cache |
| US20090144507A1 (en) * | 2007-12-04 | 2009-06-04 | International Business Machines Corporation | APPARATUS AND METHOD FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS |
| US7962695B2 (en) * | 2007-12-04 | 2011-06-14 | International Business Machines Corporation | Method and system for integrating SRAM and DRAM architecture in set associative cache |
| CN103559142B (zh) * | 2013-11-05 | 2017-03-08 | 中国科学院声学研究所 | 动态随机访问存储器的刷新方法 |
| US10811076B1 (en) * | 2019-06-29 | 2020-10-20 | Intel Corporation | Battery life based on inhibited memory refreshes |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5148546A (en) * | 1991-04-22 | 1992-09-15 | Blodgett Greg A | Method and system for minimizing power demands on portable computers and the like by refreshing selected dram cells |
| IL121044A (en) * | 1996-07-15 | 2000-09-28 | Motorola Inc | Dynamic memory device |
-
2002
- 2002-09-11 US US10/242,878 patent/US20030053361A1/en not_active Abandoned
- 2002-09-19 CA CA002461018A patent/CA2461018A1/en not_active Abandoned
- 2002-09-19 JP JP2003529478A patent/JP2005528717A/ja not_active Withdrawn
- 2002-09-19 BR BRPI0212659-1A patent/BR0212659A/pt not_active IP Right Cessation
- 2002-09-19 RU RU2004111785/09A patent/RU2004111785A/ru not_active Application Discontinuation
- 2002-09-19 WO PCT/US2002/030000 patent/WO2003025947A2/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| US20030053361A1 (en) | 2003-03-20 |
| JP2005528717A (ja) | 2005-09-22 |
| WO2003025947A3 (en) | 2003-11-13 |
| RU2004111785A (ru) | 2005-10-20 |
| WO2003025947A2 (en) | 2003-03-27 |
| BR0212659A (pt) | 2007-11-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100771059B1 (ko) | 복수의 저소비 전력 모드를 구비한 반도체 기억 장치 | |
| US8684597B2 (en) | Thermal sensor having toggle control | |
| JP2000216690A (ja) | 増幅器の動作パラメ―タを動的に変化させるシステムおよび方法 | |
| US7272065B2 (en) | Compensated refresh oscillator | |
| US20030053361A1 (en) | EDRAM based architecture | |
| US6948029B2 (en) | DRAM device and refresh control method therefor | |
| GB2080585A (en) | Semiconductor integrated circuit with reduced power consumption | |
| US7292488B2 (en) | Temperature dependent self-refresh module for a memory device | |
| US7142478B2 (en) | Clock stop detector | |
| KR100664641B1 (ko) | 셀 탐색 방법, 통신 동기화 장치, 휴대형 단말 장치, 및기록 매체 | |
| US5027327A (en) | Semiconductor memory | |
| US8159885B2 (en) | Refresh control circuit and semiconductor memory device and memory system including the same | |
| JP7731977B2 (ja) | 通信バス制御を介するコンピューティングデバイス内の省電力技術 | |
| US7969807B2 (en) | Memory that retains data when switching partial array self refresh settings | |
| US11984149B2 (en) | Memory retention for radio device | |
| US6522900B1 (en) | Method for displaying battery voltage in TDMA radio terminal | |
| US12468377B2 (en) | Processors including power control circuits to reduce a no-load voltage to save power and increase longevity and related methods | |
| US6857042B1 (en) | Method for refreshing a dynamic memory | |
| US20230047577A1 (en) | Multi-mode antenna tuner circuit and related apparatus | |
| US20250106835A1 (en) | Enhanced coexistence in multi link scenarios of wlan protocols | |
| JPH0955781A (ja) | 携帯電話機 | |
| US20180343619A1 (en) | Timer for low-power communications systems | |
| US7012843B2 (en) | Device for driving a memory cell of a memory module by means of a charge store | |
| US10788883B2 (en) | Timer for low-power communications systems | |
| US6909657B2 (en) | Pseudostatic memory circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FZDE | Dead |