BR0109423A - Método e aparelho para controlar a energia e o desempenho do processador para os sistemas de processador de laço de bloqueio de fase (pll) único - Google Patents

Método e aparelho para controlar a energia e o desempenho do processador para os sistemas de processador de laço de bloqueio de fase (pll) único

Info

Publication number
BR0109423A
BR0109423A BR0109423-8A BR0109423A BR0109423A BR 0109423 A BR0109423 A BR 0109423A BR 0109423 A BR0109423 A BR 0109423A BR 0109423 A BR0109423 A BR 0109423A
Authority
BR
Brazil
Prior art keywords
pll
single phase
phase lock
performance
cpu
Prior art date
Application number
BR0109423-8A
Other languages
English (en)
Other versions
BR0109423B1 (pt
Inventor
Sung-Soo Cho
Satchitanand Jain
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR0109423A publication Critical patent/BR0109423A/pt
Publication of BR0109423B1 publication Critical patent/BR0109423B1/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

"MéTODO E APARELHO PARA CONTROLAR A ENERGIA E O DESEMPENHO DO PROCESSADOR PARA OS SISTEMAS DE PROCESSADOR DE LAçO DE BLOQUEIO DE FASE (PLL) úNICO". A invenção refere-se a um circuito integrado que contém uma unidade de processamento central ("CPU"), um anel central de controle gráfico ("GCH"), um anel central de controle de memória ("MCH"), e um laço de bloqueio de fase ("PLL"). O GCH, o MCH, e o PLL estão acoplados na CPU. O MCH controla as transações de memória. O PLL está configurado para permitir que a CPU opere em mais do que um estado de consumo de energia.
BRPI0109423-8A 2000-03-24 2001-03-06 Circuito integrado e método para controlar a energia e o desempenho do processador para os sistemas de processador de laço de bloqueio de fase (pll) único BR0109423B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/534,187 2000-03-24
US09/534,187 US6442697B1 (en) 2000-03-24 2000-03-24 Method and apparatus to control processor power and performance for single phase lock loop (PLL) processor systems
PCT/US2001/007216 WO2001073534A2 (en) 2000-03-24 2001-03-06 Method and apparatus to control processor power and performance for single phase lock loop (pll) processor systems

Publications (2)

Publication Number Publication Date
BR0109423A true BR0109423A (pt) 2002-12-10
BR0109423B1 BR0109423B1 (pt) 2014-06-24

Family

ID=24129031

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0109423-8A BR0109423B1 (pt) 2000-03-24 2001-03-06 Circuito integrado e método para controlar a energia e o desempenho do processador para os sistemas de processador de laço de bloqueio de fase (pll) único

Country Status (10)

Country Link
US (2) US6442697B1 (pt)
EP (1) EP1269297B1 (pt)
CN (1) CN1246752C (pt)
AT (1) ATE367604T1 (pt)
AU (1) AU2001243467A1 (pt)
BR (1) BR0109423B1 (pt)
DE (1) DE60129423T2 (pt)
HK (1) HK1049534B (pt)
TW (1) TWI238932B (pt)
WO (1) WO2001073534A2 (pt)

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JP3877518B2 (ja) 2000-12-13 2007-02-07 松下電器産業株式会社 プロセッサの電力制御装置
US20020138159A1 (en) * 2001-03-26 2002-09-26 Atkinson Lee W. Temperature responsive power supply to minimize power consumption of digital logic without reducing system performance
US7149909B2 (en) * 2002-05-09 2006-12-12 Intel Corporation Power management for an integrated graphics device
CN100424616C (zh) * 2002-11-26 2008-10-08 精英电脑股份有限公司 可携式计算机电源管理的方法
US20050144341A1 (en) * 2003-12-31 2005-06-30 Schmidt Daren J. Buffer management via non-data symbol processing for a point to point link
US9323571B2 (en) * 2004-02-06 2016-04-26 Intel Corporation Methods for reducing energy consumption of buffered applications using simultaneous multi-threading processor
US7277990B2 (en) 2004-09-30 2007-10-02 Sanjeev Jain Method and apparatus providing efficient queue descriptor memory access
US20060067348A1 (en) * 2004-09-30 2006-03-30 Sanjeev Jain System and method for efficient memory access of queue control data structures
US7418543B2 (en) 2004-12-21 2008-08-26 Intel Corporation Processor having content addressable memory with command ordering
US7555630B2 (en) 2004-12-21 2009-06-30 Intel Corporation Method and apparatus to provide efficient communication between multi-threaded processing elements in a processor unit
US7467256B2 (en) * 2004-12-28 2008-12-16 Intel Corporation Processor having content addressable memory for block-based queue structures
US8044697B2 (en) * 2006-06-29 2011-10-25 Intel Corporation Per die temperature programming for thermally efficient integrated circuit (IC) operation
CN101414208B (zh) * 2007-10-16 2011-07-13 华硕电脑股份有限公司 电能分享电路
US8862786B2 (en) * 2009-08-31 2014-10-14 International Business Machines Corporation Program execution with improved power efficiency
US8850250B2 (en) * 2010-06-01 2014-09-30 Intel Corporation Integration of processor and input/output hub
US8782456B2 (en) 2010-06-01 2014-07-15 Intel Corporation Dynamic and idle power reduction sequence using recombinant clock and power gating
US9146610B2 (en) 2010-09-25 2015-09-29 Intel Corporation Throttling integrated link
US10162405B2 (en) * 2015-06-04 2018-12-25 Intel Corporation Graphics processor power management contexts and sequential control loops
US10444817B2 (en) * 2017-04-17 2019-10-15 Intel Corporation System, apparatus and method for increasing performance in a processor during a voltage ramp
US10761584B2 (en) 2018-03-16 2020-09-01 Vigyanlabs Innovations Private Limited System and method to enable prediction-based power management
TWI743538B (zh) * 2019-08-21 2021-10-21 群聯電子股份有限公司 連接介面電路、記憶體儲存裝置及訊號產生方法

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US4847870A (en) * 1987-11-25 1989-07-11 Siemens Transmission Systems, Inc. High resolution digital phase-lock loop circuit
US5153535A (en) * 1989-06-30 1992-10-06 Poget Computer Corporation Power supply and oscillator for a computer system providing automatic selection of supply voltage and frequency
JP2770656B2 (ja) * 1992-05-11 1998-07-02 ヤマハ株式会社 集積回路装置
EP1005010A3 (en) * 1994-03-16 2001-10-24 Brooktree Corporation Method for processing data in a multimedia graphics system
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US5740454A (en) * 1995-12-20 1998-04-14 Compaq Computer Corporation Circuit for setting computer system bus signals to predetermined states in low power mode
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US6240152B1 (en) * 1998-08-18 2001-05-29 Sun Microsystems, Inc. Apparatus and method for switching frequency modes in a phase locked loop system

Also Published As

Publication number Publication date
TWI238932B (en) 2005-09-01
BR0109423B1 (pt) 2014-06-24
DE60129423T2 (de) 2008-04-17
US6574738B2 (en) 2003-06-03
HK1049534B (zh) 2008-03-07
EP1269297A2 (en) 2003-01-02
WO2001073534A3 (en) 2002-09-26
ATE367604T1 (de) 2007-08-15
US20020188884A1 (en) 2002-12-12
DE60129423D1 (de) 2007-08-30
CN1418335A (zh) 2003-05-14
WO2001073534A2 (en) 2001-10-04
WO2001073534A8 (en) 2002-05-23
US6442697B1 (en) 2002-08-27
AU2001243467A1 (en) 2001-10-08
EP1269297B1 (en) 2007-07-18
HK1049534A1 (en) 2003-05-16
CN1246752C (zh) 2006-03-22

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Legal Events

Date Code Title Description
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 10 (DEZ) ANOS CONTADOS A PARTIR DE 24/06/2014, OBSERVADAS AS CONDICOES LEGAIS.

B21F Lapse acc. art. 78, item iv - on non-payment of the annual fees in time

Free format text: REFERENTE A 16A ANUIDADE.

B24J Lapse because of non-payment of annual fees (definitively: art 78 iv lpi, resolution 113/2013 art. 12)