BR0107336A - Sistema e método de processamento de dados, programa de computador, e mìdia de gravação - Google Patents

Sistema e método de processamento de dados, programa de computador, e mìdia de gravação

Info

Publication number
BR0107336A
BR0107336A BR0107336-2A BR0107336A BR0107336A BR 0107336 A BR0107336 A BR 0107336A BR 0107336 A BR0107336 A BR 0107336A BR 0107336 A BR0107336 A BR 0107336A
Authority
BR
Brazil
Prior art keywords
data
gsms
computer program
recording media
processing system
Prior art date
Application number
BR0107336-2A
Other languages
English (en)
Inventor
Hitoshi Ebihara
Original Assignee
Sony Computer Entertainment Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Computer Entertainment Inc filed Critical Sony Computer Entertainment Inc
Publication of BR0107336A publication Critical patent/BR0107336A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7864—Architectures of general purpose stored program computers comprising a single central processing unit with memory on more than one IC chip
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory

Abstract

"SISTEMA E MéTODO DE PROCESSAMENTO DE DADOS, PROGRAMA DE COMPUTADOR, E MìDIA DE GRAVAçãO". Que apresenta uma tecnologia de comunicação de dados para aumentar a eficiência de uma cooperação de duas ou mais unidades de processamento de, informações (GSM) para um processamento mais sofisticado. De acordo com a presente invenção, são empregadas quatro GSMs 1, um sub-MG (fundidor) 3 para fundir os dados fornecidos pelas GSMs 1, e um MG principal 200 para fundir os dados fornecidos pelas quatro sub-MGs 3. Os dados fornecidos pelas GSMs 1 são armazenados em paralelo em um registro em uma base de unidade de comprimento. Os dados armazenados no registro são lidos então em série na base de unidade de comprimento para formar os dados seriais. Quando os dados seriais contêm dados modificados, os dados auxiliares para identificar aqueles modificados são adicionados a uma parte predeterminada dos dados seriais e fornecidos ao MG principal 200. Por outro lado, os dados paralelos a serem fornecidos de uma SYNC principal 300 a cada GSM 1 são copiados, e as cópias dos mesmos dados paralelos são propagadas a todas as GSMs 1 ao mesmo tempo.
BR0107336-2A 2000-10-10 2001-10-09 Sistema e método de processamento de dados, programa de computador, e mìdia de gravação BR0107336A (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2000309788 2000-10-10
JP2001306961A JP3580789B2 (ja) 2000-10-10 2001-10-02 データ通信システム及び方法、コンピュータプログラム、記録媒体
PCT/JP2001/008861 WO2002031771A1 (fr) 2000-10-10 2001-10-09 Systeme et procede de communication de donnees, programme d'ordinateur et support d'enregistrement

Publications (1)

Publication Number Publication Date
BR0107336A true BR0107336A (pt) 2002-08-27

Family

ID=26601819

Family Applications (1)

Application Number Title Priority Date Filing Date
BR0107336-2A BR0107336A (pt) 2000-10-10 2001-10-09 Sistema e método de processamento de dados, programa de computador, e mìdia de gravação

Country Status (11)

Country Link
US (1) US6952213B2 (pt)
EP (1) EP1326208A4 (pt)
JP (1) JP3580789B2 (pt)
KR (1) KR20020059840A (pt)
CN (1) CN1255765C (pt)
AU (1) AU9236901A (pt)
BR (1) BR0107336A (pt)
CA (1) CA2392536A1 (pt)
MX (1) MXPA02005309A (pt)
TW (1) TWI242722B (pt)
WO (1) WO2002031771A1 (pt)

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US8085273B2 (en) 2003-11-19 2011-12-27 Lucid Information Technology, Ltd Multi-mode parallel graphics rendering system employing real-time automatic scene profiling and mode control
JP2007512613A (ja) * 2003-11-19 2007-05-17 ルシッド インフォメーション テクノロジー リミテッド Ｐｃバス上の多重３−ｄグラフィックパイプラインのための方法およびシステム
WO2006117683A2 (en) * 2005-01-25 2006-11-09 Lucid Information Technology, Ltd. Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic construction
US20090027383A1 (en) * 2003-11-19 2009-01-29 Lucid Information Technology, Ltd. Computing system parallelizing the operation of multiple graphics processing pipelines (GPPLs) and supporting depth-less based image recomposition
US8497865B2 (en) * 2006-12-31 2013-07-30 Lucid Information Technology, Ltd. Parallel graphics system employing multiple graphics processing pipelines with multiple graphics processing units (GPUS) and supporting an object division mode of parallel graphics processing using programmable pixel or vertex processing resources provided with the GPUS
US7777748B2 (en) 2003-11-19 2010-08-17 Lucid Information Technology, Ltd. PC-level computing system with a multi-mode parallel graphics rendering subsystem employing an automatic mode controller, responsive to performance data collected during the run-time of graphics applications
US7961194B2 (en) 2003-11-19 2011-06-14 Lucid Information Technology, Ltd. Method of controlling in real time the switching of modes of parallel operation of a multi-mode parallel graphics processing subsystem embodied within a host computing system
US20090096798A1 (en) * 2005-01-25 2009-04-16 Reuven Bakalash Graphics Processing and Display System Employing Multiple Graphics Cores on a Silicon Chip of Monolithic Construction
US8645403B2 (en) * 2006-02-03 2014-02-04 Autodesk, Inc. Database-managed rendering
US8024356B2 (en) * 2006-02-03 2011-09-20 Autodesk, Inc. Database-managed image processing
US8766995B2 (en) 2006-04-26 2014-07-01 Qualcomm Incorporated Graphics system with configurable caches
CN100487731C (zh) * 2006-05-12 2009-05-13 深圳迈瑞生物医疗电子股份有限公司 硬件加速显示的并行处理装置及并行处理方法
US20070268289A1 (en) * 2006-05-16 2007-11-22 Chun Yu Graphics system with dynamic reposition of depth engine
US8884972B2 (en) 2006-05-25 2014-11-11 Qualcomm Incorporated Graphics processor with arithmetic and elementary function units
US8869147B2 (en) * 2006-05-31 2014-10-21 Qualcomm Incorporated Multi-threaded processor with deferred thread output control
US8644643B2 (en) 2006-06-14 2014-02-04 Qualcomm Incorporated Convolution filtering in a graphics processor
US8766996B2 (en) * 2006-06-21 2014-07-01 Qualcomm Incorporated Unified virtual addressed register file
JP2009150726A (ja) * 2007-12-19 2009-07-09 Panasonic Corp 半導体装置
US8139840B1 (en) 2008-04-10 2012-03-20 Kla-Tencor Corporation Inspection system and method for high-speed serial data transfer
KR101511110B1 (ko) * 2014-12-29 2015-04-17 (주)윌넷 엘이디 시스템의 동작 모니터링 방법
KR20180002786A (ko) 2015-06-05 2018-01-08 애플 인크. 디스플레이 패널에 대한 방출 제어 장치들 및 방법들
JP6966943B2 (ja) * 2015-06-10 2021-11-17 アップル インコーポレイテッドApple Inc. ディスプレイパネルの冗長スキーム

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JPH0827773B2 (ja) * 1992-10-23 1996-03-21 インターナショナル・ビジネス・マシーンズ・コーポレイション データ経路を使用可能にする方法、装置およびデータ処理システム
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Also Published As

Publication number Publication date
CA2392536A1 (en) 2002-04-18
CN1393001A (zh) 2003-01-22
US6952213B2 (en) 2005-10-04
CN1255765C (zh) 2006-05-10
MXPA02005309A (es) 2002-12-11
US20020059302A1 (en) 2002-05-16
WO2002031771A1 (fr) 2002-04-18
AU9236901A (en) 2002-04-22
JP2002202957A (ja) 2002-07-19
KR20020059840A (ko) 2002-07-13
JP3580789B2 (ja) 2004-10-27
TWI242722B (en) 2005-11-01
EP1326208A1 (en) 2003-07-09
EP1326208A4 (en) 2007-06-06

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Legal Events

Date Code Title Description
B11A Dismissal acc. art.33 of ipl - examination not requested within 36 months of filing
B11Y Definitive dismissal - extension of time limit for request of examination expired [chapter 11.1.1 patent gazette]