BR0014819A - Método de produção de placas de chip sem contato e de produção de unidades elétricas que consistem em chips com elementos de contato - Google Patents

Método de produção de placas de chip sem contato e de produção de unidades elétricas que consistem em chips com elementos de contato

Info

Publication number
BR0014819A
BR0014819A BR0014819-9A BR0014819A BR0014819A BR 0014819 A BR0014819 A BR 0014819A BR 0014819 A BR0014819 A BR 0014819A BR 0014819 A BR0014819 A BR 0014819A
Authority
BR
Brazil
Prior art keywords
chips
contact
producing
electrical units
contact elements
Prior art date
Application number
BR0014819-9A
Other languages
English (en)
Inventor
Andreas Plettner
Original Assignee
Andreas Plettner
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19948555A external-priority patent/DE19948555A1/de
Application filed by Andreas Plettner filed Critical Andreas Plettner
Publication of BR0014819A publication Critical patent/BR0014819A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Credit Cards Or The Like (AREA)
  • Wire Bonding (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Manufacture Of Switches (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

"MéTODO DE PRODUçãO DE PLACAS DE CHIP SEM CONTATO E DE PRODUçãO DE UNIDADES ELéTRICAS QUE CONSISTEM EM CHIPS COM ELEMENTOS DE CONTATO". Trata-se de um método de produção de placas de chip sem contato e de produção de unidades elétricas que consistem em chips com elementos de contato, sendo que os elementos de contato são adequados para a conexão direta com os terminais de contato de componentes elétricos externos de uma maneira eletricamente condutora, onde a conexão dos elementos de contato com os chips é efetuada antes que os chips individuais sejam removidos do agrupamento predefinido pela pastilha e que consiste em fileiras e colunas, e os elementos de contato são feitos de uma folha de plástico metalizada ou uma folha metálica a ser aplicada nos chips.
BR0014819-9A 1999-10-08 2000-10-06 Método de produção de placas de chip sem contato e de produção de unidades elétricas que consistem em chips com elementos de contato BR0014819A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19948555A DE19948555A1 (de) 1999-12-03 1999-10-08 Verfahren zur Herstellung kontaktloser Chipkarten sowie zur Herstellung von elektrischen Einheiten, bestehend aus Chips mit Kontaktelementen
PCT/EP2000/009818 WO2001027871A2 (de) 1999-10-08 2000-10-06 Verfahren zur herstellung kontaktloser chipkarten sowie zur herstellung von elektrischen einheiten, bestehend aus chips mit kontaktelementen

Publications (1)

Publication Number Publication Date
BR0014819A true BR0014819A (pt) 2002-06-11

Family

ID=7924978

Family Applications (1)

Application Number Title Priority Date Filing Date
BR0014819-9A BR0014819A (pt) 1999-10-08 2000-10-06 Método de produção de placas de chip sem contato e de produção de unidades elétricas que consistem em chips com elementos de contato

Country Status (7)

Country Link
EP (1) EP1224618B1 (pt)
JP (1) JP4733327B2 (pt)
CN (1) CN1238811C (pt)
AT (1) ATE237849T1 (pt)
AU (1) AU7662700A (pt)
BR (1) BR0014819A (pt)
WO (1) WO2001027871A2 (pt)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1771506A (zh) * 2003-05-28 2006-05-10 株式会社日立制作所 无线识别半导体装置及其制造方法
FR2940486B1 (fr) * 2008-12-22 2011-02-11 Commissariat Energie Atomique Procede de fabrication d'un assemblage de puces a moyens d'emission-reception radiofrequence reliees mecaniquement au moyen d'un ruban et assemblage

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS514628B1 (pt) * 1970-02-05 1976-02-13
JPS624351A (ja) * 1985-06-29 1987-01-10 Toshiba Corp 半導体キヤリアの製造方法
JPH04127442A (ja) * 1990-09-18 1992-04-28 Sharp Corp ダイボンディング装置
JPH08125154A (ja) * 1994-10-24 1996-05-17 Olympus Optical Co Ltd 半導体装置の製造方法
JPH10209226A (ja) * 1997-01-23 1998-08-07 Mitsubishi Electric Corp 半導体部材、及び半導体チップ
FR2761527B1 (fr) * 1997-03-25 1999-06-04 Gemplus Card Int Procede de fabrication de carte sans contact avec connexion d'antenne par fils soudes
JPH1140522A (ja) * 1997-07-17 1999-02-12 Rohm Co Ltd 半導体ウエハの製造方法、この方法により作製された半導体ウエハ、半導体チップの製造方法、およびこの方法により製造された半導体チップ、ならびにこの半導体チップを備えたｉｃカード
JP3173493B2 (ja) * 1999-02-18 2001-06-04 日本電気株式会社 半導体装置及び半導体装置の製造方法

Also Published As

Publication number Publication date
EP1224618B1 (de) 2003-04-16
CN1238811C (zh) 2006-01-25
AU7662700A (en) 2001-04-23
WO2001027871A3 (de) 2001-11-01
JP4733327B2 (ja) 2011-07-27
EP1224618A2 (de) 2002-07-24
JP2003511869A (ja) 2003-03-25
CN1384951A (zh) 2002-12-11
WO2001027871A2 (de) 2001-04-19
ATE237849T1 (de) 2003-05-15

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Legal Events

Date Code Title Description
B11A Dismissal acc. art.33 of ipl - examination not requested within 36 months of filing
B11Y Definitive dismissal - extension of time limit for request of examination expired [chapter 11.1.1 patent gazette]