BR0012562A - Arquitetura de amplificador paralelo utilizando-se técnicas digitais de controle de fase - Google Patents

Arquitetura de amplificador paralelo utilizando-se técnicas digitais de controle de fase

Info

Publication number
BR0012562A
BR0012562A BR0012562-8A BR0012562A BR0012562A BR 0012562 A BR0012562 A BR 0012562A BR 0012562 A BR0012562 A BR 0012562A BR 0012562 A BR0012562 A BR 0012562A
Authority
BR
Brazil
Prior art keywords
phase control
digital phase
control techniques
parallel amplifier
amplifier architecture
Prior art date
Application number
BR0012562-8A
Other languages
English (en)
Inventor
Peter D Heidmann
Joseph P Burke
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR0012562A publication Critical patent/BR0012562A/pt

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/211Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0294Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using vector summing of two or more constant amplitude phase-modulated signals
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/60Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
    • H03F3/602Combinations of several amplifiers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2201/00Indexing scheme relating to details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements covered by H03F1/00
    • H03F2201/32Indexing scheme relating to modifications of amplifiers to reduce non-linear distortion
    • H03F2201/3215To increase the output power or efficiency
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2203/00Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/20Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F2203/21Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F2203/211Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H03F2203/21163An output signal dependant signal being measured by power measuring, e.g. by an inductive coupler, at the output of a power amplifier

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Transmitters (AREA)

Abstract

"ARQUITETURA DE AMPLIFICADOR PARALELO UTILIZANDO-SE TéCNICAS DIGITAIS DE CONTROLE DE FASE". Um método e aparelho melhorados para utilizar amplificadores paralelos para amplificar eficientemente um sinal de informação são revelados. O aparelho melhorado utiliza técnicas de manipulação de sinal digitais ao otimizar a fase dos sinais de entrada convertidos em freq³ência (upconverted) providos a cada um dos amplificadores paralelos. A fase e a amplitude dos sinais de entrada são ajustadas de forma que a potência medida na saída de um combinador (402) seja maximizada ao ser comparada à soma da potência dos sinais de entrada do combinador (120).
BR0012562-8A 1999-07-20 2000-07-18 Arquitetura de amplificador paralelo utilizando-se técnicas digitais de controle de fase BR0012562A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/357,695 US6799020B1 (en) 1999-07-20 1999-07-20 Parallel amplifier architecture using digital phase control techniques
PCT/US2000/019605 WO2001006643A1 (en) 1999-07-20 2000-07-18 Parallel amplifier architecture using digital phase control techniques

Publications (1)

Publication Number Publication Date
BR0012562A true BR0012562A (pt) 2003-07-01

Family

ID=23406666

Family Applications (1)

Application Number Title Priority Date Filing Date
BR0012562-8A BR0012562A (pt) 1999-07-20 2000-07-18 Arquitetura de amplificador paralelo utilizando-se técnicas digitais de controle de fase

Country Status (13)

Country Link
US (1) US6799020B1 (pt)
EP (1) EP1201027B1 (pt)
JP (1) JP2003527771A (pt)
KR (2) KR100833832B1 (pt)
CN (1) CN1218477C (pt)
AT (1) ATE356466T1 (pt)
AU (1) AU6353800A (pt)
BR (1) BR0012562A (pt)
DE (1) DE60033820T2 (pt)
DK (1) DK1201027T3 (pt)
ES (1) ES2282128T3 (pt)
HK (1) HK1052589A1 (pt)
WO (1) WO2001006643A1 (pt)

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Also Published As

Publication number Publication date
KR20020056873A (ko) 2002-07-10
EP1201027B1 (en) 2007-03-07
EP1201027A1 (en) 2002-05-02
WO2001006643A1 (en) 2001-01-25
DK1201027T3 (da) 2007-12-03
KR100833832B1 (ko) 2008-06-02
AU6353800A (en) 2001-02-05
ES2282128T3 (es) 2007-10-16
DE60033820D1 (de) 2007-04-19
HK1052589A1 (en) 2003-09-19
JP2003527771A (ja) 2003-09-16
KR20070024684A (ko) 2007-03-02
ATE356466T1 (de) 2007-03-15
KR100875866B1 (ko) 2008-12-26
US6799020B1 (en) 2004-09-28
DE60033820T2 (de) 2007-11-15
CN1218477C (zh) 2005-09-07
CN1409894A (zh) 2003-04-09

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B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

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B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

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