BE835653A - Configuration de circuit de decodage a transistors a effet de champ de type mos a espacement minimum - Google Patents

Configuration de circuit de decodage a transistors a effet de champ de type mos a espacement minimum

Info

Publication number
BE835653A
BE835653A BE161939A BE161939A BE835653A BE 835653 A BE835653 A BE 835653A BE 161939 A BE161939 A BE 161939A BE 161939 A BE161939 A BE 161939A BE 835653 A BE835653 A BE 835653A
Authority
BE
Belgium
Prior art keywords
mos
configuration
effect transistor
type field
decoding circuit
Prior art date
Application number
BE161939A
Other languages
English (en)
French (fr)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of BE835653A publication Critical patent/BE835653A/xx

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
BE161939A 1974-12-23 1975-11-17 Configuration de circuit de decodage a transistors a effet de champ de type mos a espacement minimum BE835653A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US535748A US3909808A (en) 1974-12-23 1974-12-23 Minimum pitch mosfet decoder circuit configuration

Publications (1)

Publication Number Publication Date
BE835653A true BE835653A (fr) 1976-03-16

Family

ID=24135594

Family Applications (1)

Application Number Title Priority Date Filing Date
BE161939A BE835653A (fr) 1974-12-23 1975-11-17 Configuration de circuit de decodage a transistors a effet de champ de type mos a espacement minimum

Country Status (11)

Country Link
US (1) US3909808A (ja)
JP (1) JPS5516336B2 (ja)
BE (1) BE835653A (ja)
BR (1) BR7508618A (ja)
CA (1) CA1058754A (ja)
CH (1) CH594319A5 (ja)
FR (1) FR2296308A1 (ja)
GB (1) GB1522638A (ja)
IT (1) IT1049900B (ja)
NL (1) NL7514624A (ja)
SE (1) SE410246B (ja)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4144587A (en) * 1976-07-22 1979-03-13 Tokyo Shibaura Electric Co., Ltd. Counting level "1" bits to minimize ROM active elements
JPS5352027A (en) * 1976-10-22 1978-05-12 Mitsubishi Electric Corp Decoder circuit
JPS5833633B2 (ja) * 1978-08-25 1983-07-21 シャープ株式会社 Ｍｏｓトランジスタ・デコ−ダ
US4200917A (en) * 1979-03-12 1980-04-29 Motorola, Inc. Quiet column decoder
JPS5847796B2 (ja) * 1979-05-26 1983-10-25 富士通株式会社 半導体メモリ装置
US4447895A (en) * 1979-10-04 1984-05-08 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory device
US4259731A (en) * 1979-11-14 1981-03-31 Motorola, Inc. Quiet row selection circuitry
JPS5683891A (en) * 1979-12-13 1981-07-08 Fujitsu Ltd Semiconductor storage device
US4419741A (en) * 1980-01-28 1983-12-06 Rca Corporation Read only memory (ROM) having high density memory array with on pitch decoder circuitry
IT1135037B (it) * 1980-01-28 1986-08-20 Rca Corp Selettore di linee per la decodificazione in passo di linee multiple di ingresso
US4287576A (en) * 1980-03-26 1981-09-01 International Business Machines Corporation Sense amplifying system for memories with small cells
JPS6042554B2 (ja) * 1980-12-24 1985-09-24 富士通株式会社 Ｃｍｏｓメモリデコ−ダ回路
JPS5873097A (ja) * 1981-10-27 1983-05-02 Nec Corp デコ−ダ−回路
US4514829A (en) * 1982-12-30 1985-04-30 International Business Machines Corporation Word line decoder and driver circuits for high density semiconductor memory
JPH0762960B2 (ja) * 1984-12-28 1995-07-05 日本電気株式会社 半導体回路
US9349738B1 (en) * 2008-02-04 2016-05-24 Broadcom Corporation Content addressable memory (CAM) device having substrate array line structure

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3514765A (en) * 1969-05-23 1970-05-26 Shell Oil Co Sense amplifier comprising cross coupled mosfet's operating in a race mode for single device per bit mosfet memories
US3821715A (en) * 1973-01-22 1974-06-28 Intel Corp Memory system for a multi chip digital computer

Also Published As

Publication number Publication date
FR2296308A1 (fr) 1976-07-23
CH594319A5 (ja) 1978-01-13
SE410246B (sv) 1979-10-01
DE2557006A1 (de) 1976-07-08
JPS5516336B2 (ja) 1980-05-01
SE7514597L (sv) 1976-06-24
CA1058754A (en) 1979-07-17
DE2557006B2 (de) 1977-02-17
FR2296308B1 (ja) 1977-12-16
NL7514624A (nl) 1976-06-25
BR7508618A (pt) 1976-08-24
GB1522638A (en) 1978-08-23
JPS5184537A (ja) 1976-07-23
IT1049900B (it) 1981-02-10
US3909808A (en) 1975-09-30

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Legal Events

Date Code Title Description
RE Patent lapsed

Owner name: INTRNATIONAL BUSINESS MACHINES CORP.

Effective date: 19841117