AU4072899A - Software configurable technique for prioritizing interrupts in a microprocessor-based system - Google Patents

Software configurable technique for prioritizing interrupts in a microprocessor-based system

Info

Publication number
AU4072899A
AU4072899A AU40728/99A AU4072899A AU4072899A AU 4072899 A AU4072899 A AU 4072899A AU 40728/99 A AU40728/99 A AU 40728/99A AU 4072899 A AU4072899 A AU 4072899A AU 4072899 A AU4072899 A AU 4072899A
Authority
AU
Australia
Prior art keywords
registers
logical
interrupts
microprocessor
gates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU40728/99A
Other languages
English (en)
Inventor
Steven R. Cox
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Electronics Inc
Original Assignee
Sony Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Electronics Inc filed Critical Sony Electronics Inc
Publication of AU4072899A publication Critical patent/AU4072899A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Logic Circuits (AREA)
  • Hardware Redundancy (AREA)
AU40728/99A 1998-05-20 1999-05-10 Software configurable technique for prioritizing interrupts in a microprocessor-based system Abandoned AU4072899A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09082432 1998-05-20
US09/082,432 US6081867A (en) 1998-05-20 1998-05-20 Software configurable technique for prioritizing interrupts in a microprocessor-based system
PCT/US1999/010171 WO1999060488A1 (en) 1998-05-20 1999-05-10 Software configurable technique for prioritizing interrupts in a microprocessor-based system

Publications (1)

Publication Number Publication Date
AU4072899A true AU4072899A (en) 1999-12-06

Family

ID=22171186

Family Applications (1)

Application Number Title Priority Date Filing Date
AU40728/99A Abandoned AU4072899A (en) 1998-05-20 1999-05-10 Software configurable technique for prioritizing interrupts in a microprocessor-based system

Country Status (7)

Country Link
US (1) US6081867A (enExample)
EP (1) EP1080422B1 (enExample)
JP (1) JP2002516433A (enExample)
AT (1) ATE300764T1 (enExample)
AU (1) AU4072899A (enExample)
DE (1) DE69926365T2 (enExample)
WO (1) WO1999060488A1 (enExample)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6553443B1 (en) * 1999-09-28 2003-04-22 Legerity, Inc. Method and apparatus for prioritizing interrupts in a communication system
WO2001063416A1 (en) * 2000-02-24 2001-08-30 Bops Incorporated Methods and apparatus for scalable array processor interrupt detection and response
DE10062995A1 (de) * 2000-12-16 2002-07-11 Micronas Gmbh Unterbrecher-Steuereinrichtung
DE10062996B4 (de) * 2000-12-16 2005-09-29 Micronas Gmbh Unterbrecher-Steuereinrichtung mit Prioritätsvorgabe
US6813666B2 (en) * 2001-02-12 2004-11-02 Freescale Semiconductor, Inc. Scaleable arbitration and prioritization of multiple interrupts
US6857036B2 (en) * 2001-07-17 2005-02-15 Hewlett Packard Development Company, L.P. Hardware method for implementing atomic semaphore operations using code macros
US7552261B2 (en) * 2001-10-12 2009-06-23 Mips Technologies, Inc. Configurable prioritization of core generated interrupts
US7487339B2 (en) * 2001-10-12 2009-02-03 Mips Technologies, Inc. Method and apparatus for binding shadow registers to vectored interrupts
GB2381890B (en) * 2001-11-12 2003-10-29 Mentor Graphics Testing the interrupt sources of a microprocessor
GB2381891B (en) * 2001-11-12 2003-10-29 Mentor Graphics Testing the interrupt priority levels in a microprocessor
CN1428710A (zh) * 2001-12-28 2003-07-09 希旺科技股份有限公司 多功能电子周边卡
US6993685B2 (en) * 2002-09-12 2006-01-31 Hewlett-Packard Development Company, L.P. Technique for testing processor interrupt logic
US7492545B1 (en) 2003-03-10 2009-02-17 Marvell International Ltd. Method and system for automatic time base adjustment for disk drive servo controllers
US7870346B2 (en) 2003-03-10 2011-01-11 Marvell International Ltd. Servo controller interface module for embedded disk controllers
US7039771B1 (en) 2003-03-10 2006-05-02 Marvell International Ltd. Method and system for supporting multiple external serial port devices using a serial port controller in embedded disk controllers
US7219182B2 (en) 2003-03-10 2007-05-15 Marvell International Ltd. Method and system for using an external bus controller in embedded disk controllers
JP4017646B2 (ja) * 2003-06-20 2007-12-05 富士通株式会社 割り込み制御方法、割り込み制御装置及び割り込み制御プログラム
US7206884B2 (en) * 2004-02-11 2007-04-17 Arm Limited Interrupt priority control within a nested interrupt system
US7607133B2 (en) * 2004-02-11 2009-10-20 Arm Limited Interrupt processing control
US7516252B2 (en) * 2005-06-08 2009-04-07 Intel Corporation Port binding scheme to create virtual host bus adapter in a virtualized multi-operating system platform environment
US7415557B2 (en) * 2006-06-06 2008-08-19 Honeywell International Inc. Methods and system for providing low latency and scalable interrupt collection
US9946668B1 (en) * 2007-01-10 2018-04-17 The Mathworks, Inc. Automatic prioritization of interrupts in a modeling environment
US7613860B2 (en) * 2007-07-02 2009-11-03 International Business Machines Corporation Prioritization of interrupts in a storage controller based on interrupt control directives received from hosts
US7617345B2 (en) * 2007-07-02 2009-11-10 International Business Machines Corporation Prioritization of interrupts in a storage controller based on interrupt control directives received from hosts
US7685347B2 (en) * 2007-12-11 2010-03-23 Xilinx, Inc. Interrupt controller for invoking service routines with associated priorities
US8504750B1 (en) * 2009-06-23 2013-08-06 Qlogic, Corporation System and method to process event reporting in an adapter
US9189283B2 (en) 2011-03-03 2015-11-17 Hewlett-Packard Development Company, L.P. Task launching on hardware resource for client
US8738830B2 (en) 2011-03-03 2014-05-27 Hewlett-Packard Development Company, L.P. Hardware interrupt processing circuit
US9645823B2 (en) 2011-03-03 2017-05-09 Hewlett-Packard Development Company, L.P. Hardware controller to choose selected hardware entity and to execute instructions in relation to selected hardware entity
US8661177B2 (en) * 2011-12-19 2014-02-25 Advanced Micro Devices, Inc. Method and apparatus for controlling system interrupts

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5905898A (en) * 1994-05-31 1999-05-18 Advanced Micro Devices, Inc. Apparatus and method for storing interrupt source information in an interrupt controller based upon interrupt priority
US5768599A (en) * 1995-02-28 1998-06-16 Nec Corporation Interrupt managing system for real-time operating system
US5619706A (en) * 1995-03-02 1997-04-08 Intel Corporation Method and apparatus for switching between interrupt delivery mechanisms within a multi-processor system
US5594905A (en) * 1995-04-12 1997-01-14 Microsoft Corporation Exception handler and method for handling interrupts
US5805929A (en) * 1996-01-29 1998-09-08 International Business Machines Corporation Multiple independent I/O functions on a PCMCIA card share a single interrupt request signal using an AND gate for triggering a delayed RESET signal
US5778236A (en) * 1996-05-17 1998-07-07 Advanced Micro Devices, Inc. Multiprocessing interrupt controller on I/O bus
US5819095A (en) * 1996-12-20 1998-10-06 International Business Machines Corporation Method and apparatus for allowing an interrupt controller on an adapter to control a computer system
US5787290A (en) * 1996-12-20 1998-07-28 International Business Machines Corporation Adapter with an onboard interrupt controller for controlling a computer system
US5918057A (en) * 1997-03-20 1999-06-29 Industrial Technology Research Institute Method and apparatus for dispatching multiple interrupt requests simultaneously

Also Published As

Publication number Publication date
EP1080422A1 (en) 2001-03-07
WO1999060488A1 (en) 1999-11-25
DE69926365T2 (de) 2006-05-24
EP1080422A4 (en) 2002-07-17
JP2002516433A (ja) 2002-06-04
ATE300764T1 (de) 2005-08-15
US6081867A (en) 2000-06-27
EP1080422B1 (en) 2005-07-27
DE69926365D1 (de) 2005-09-01

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase